ad7655-ep Analog Devices, Inc., ad7655-ep Datasheet

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ad7655-ep

Manufacturer Part Number
ad7655-ep
Description
Low Cost, 4-channel, 16-bit 1 Msps Pulsar Adc Ad7655-ep
Manufacturer
Analog Devices, Inc.
Datasheet
FEATURES
4-channel, 16-bit resolution ADC
2 track-and-hold amplifiers
Throughput
Analog input voltage range: 0 V to 5 V
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 5 V supply operation
Power dissipation
48-lead frame chip scale package (LFCSP)
Pin-to-pin compatible with the AD7654
Low cost
Supports defense and aerospace applications (AQEC
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
Enhanced product change notification
Qualification data available on request
APPLICATIONS
AC motor control
GENERAL DESCRIPTION
The AD7655-EP is a low cost, simultaneous sampling, dual-
channel, 16-bit, charge redistribution SAR, analog-to-digital
converter that operates from a single 5 V power supply. It
contains two low noise, wide bandwidth, track-and-hold
amplifiers that allow simultaneous sampling, a high speed
16-bit sampling ADC, an internal conversion clock, error
correction circuits, and both serial and parallel system interface
ports. Each track-and-hold has a multiplexer in front to provide
a 4-channel input ADC. The A0 multiplexer control input
allows the choice of simultaneously sampling input pairs
INA1/INB1 (A0 = low) or INA2/ INB2 (A0 = high). The part
features a very high sampling rate mode (normal) and, for low
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
1 MSPS (normal mode)
888 kSPS (impulse mode)
120 mW typical
2.6 mW @ 10 kSPS
standard)
3-phase power control
4-channel data acquisition
Uninterrupted power supplies
Communications
Low Cost, 4-Channel, 16-Bit 1 MSPS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
RESET
Table 1. PulSAR® Selection
Type/kSPS
Pseudo
Differential
True Bipolar
True
Differential
18 Bit
Multichannel/
Simultaneous
power applications, a reduced power mode (impulse) where the
power is scaled with the throughput. Operation is specified
from −55°C to +125°C.
Full details about this enhanced product are available in the
AD7655
with this data sheet.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
INAN
INBN
INA2
INB2
INA1
INB1
PD
A0
Multichannel ADC.
The AD7655-EP features 4-channel inputs with two sample-
and-hold circuits that allow simultaneous sampling.
Fast Throughput.
The AD7655-EP is a 1 MSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
Single-Supply Operation.
The AD7655-EP operates from a single 5 V supply. In impulse
mode, its power dissipation decreases with throughput.
Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangements
are compatible with both 3 V and 5 V logic.
AVDD AGND
AD7655-EP
MUX
MUX
data sheet, which should be consulted in conjunction
TRACK/HOLD
FUNCTIONAL BLOCK DIAGRAM
CALIBRATION CIRCUITRY
CONTROL LOGIC AND
×2
IMPULSE
100 to 250
AD7660/
AD7661
AD7663
AD7675
AD7678
MUX
©2010–2011 Analog Devices, Inc. All rights reserved.
REFGND
SWITCHED
CAP DAC
CNVST
REFx
CLOCK
Figure 1.
500 to 570
AD7650/
AD7652
AD7664/
AD7666
AD7665
AD7676
AD7679
AD7654
DVDD
INTERFACE
PARALLEL
PulSAR ADC
AD7655-EP
SERIAL
PORT
DGND
800 to
1000
AD7653
AD7667
AD7671
AD7677
AD7674
AD7655
16
www.analog.com
OVDD
OGND
D[15:0]
BUSY
CS
RD
BYTESWAP
SER/PAR
EOC
A/B
>1000
AD7621
AD7623
AD7641

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ad7655-ep Summary of contents

Page 1

... Fast Throughput. The AD7655- MSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. 3. Single-Supply Operation. The AD7655-EP operates from a single 5 V supply. In impulse mode, its power dissipation decreases with throughput. 4. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangements are compatible with both 3 V and 5 V logic ...

Page 2

... AD7655-EP TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 REVISION HISTORY 2/11—Rev Rev. A Removed LQFP from Features Section ......................................... 1 Removed Internal Power Dissipation (700 mW) from Table 7/10—Revision 0: Initial Version Timing Specifications ...................................................................5 Absolute Maximum Ratings ............................................................7 ESD Caution ...

Page 3

... 100 kHz IN Full-scale step 2.3 1 MSPS throughput −0.3 +2.0 −1 − 1.6 mA SINK I = −500 µA OVDD − 0.2 SOURCE Rev Page AD7655-EP , unless otherwise noted. MAX Typ Max Unit Bits REF +0 µA 2 µs 1 MSPS 2.25 µs ...

Page 4

... AD7655-EP Parameter POWER SUPPLIES Specified Performance AVDD DVDD OVDD 7 Operating Current AVDD DVDD OVDD Power Dissipation 9 TEMPERATURE RANGE Specified Performance 1 Linearity is tested using endpoints, not best fit. 2 LSB means least significant bit. With the input range, 1 LSB is 76.294 µV. ...

Page 5

... Rev Page AD7655-EP , unless otherwise noted. MAX Min Typ Max 5 2/2.25 32 1.75 1.75/2 250 10 30 1/1.25 45 0.75 250 30 1.75 250/500 ...

Page 6

... AD7655-EP Parameter SLAVE SERIAL INTERFACE MODES External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK High External SCLK Low 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load serial master read during convert mode ...

Page 7

... SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C = 26°C/W. JA 0.8V t DELAY ESD CAUTION Rev Page AD7655-EP I 1.6mA OL TO OUTPUT 1.4V PIN C L 60pF* I 500mA OH OF 10pF ...

Page 8

... When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW AGND PIN 1 AVDD BYTESWAP 4 A/B AD7655-EP 5 DGND TOP VIEW 6 (Not to Scale) IMPULSE 7 SER/PAR ...

Page 9

... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external serial clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7655-EP. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND Power-Down Input ...

Page 10

... AD7655-EP 1 Pin No. Mnemonic Type Description 35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. In impulse mode (IMPULSE = HIGH), if CNVST is held LOW when the acquisition phase (t immediately started. 37 REF AI This input pin is used to provide a reference to the converter. ...

Page 11

... Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Rev Page 0.30 0.23 0.18 PIN 1 INDICATOR 48 1 EXPOSED 5.25 PAD 5.10 SQ (BOTTOM VIEW) 4. 0.25 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-48-1 AD7655-EP ...

Page 12

... AD7655-EP NOTES ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09230-0-2/11(A) Rev Page ...

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