ad7466-kgd Analog Devices, Inc., ad7466-kgd Datasheet - Page 6

• Manufacturer Part Number: ad7466-kgd
• Description: 1.6 V, Micropower 12-bit Adc
• Manufacturer: Analog Devices, Inc.

AD7466-KGD
TIMING EXAMPLES
Figure 3 shows some of the timing parameters from Table 2 in
the Timing Specifications section.
Timing Example 1
As shown in Figure 3, f
100 kSPS gives a cycle time of t
Assuming V
4.41 μs = 4.46 μs, and t
which satisfies the requirement of 10 ns for t
fully powered up and the signal is fully acquired at Point A.
This means that the acquisition/power-up time is t
= 55 ns + 588 ns = 643 ns, satisfying the maximum requirement
of 640 ns for the power-up time.
SCLK
CS
DD
= 1.8 V, t
POINT A: THE PART IF FULLY POWERED UP WITH V
t
8
2
ACQUISITION TIME
TRACK-AND-HOLD
SCLK
= 60 ns maximum, then t
CONVERT
1
IN TRACK
= 3.4 MHz and a throughput of
CONVERT
= t
2
2
B A
+ 15(1/f
+ t
3
8
Figure 3.
+ t
SCLK
QUIET
QUIET
) = 55 ns +
4
QUIET
. The part is
AD7466-KGD
= 10 μs.
2
+ 2(1/f
t
= 5.48 μs,
CONVERT
5
SCLK
IN
Rev. 0 | Page 6 of 12
FULLY ACQUIRED.
Serial Interface Timing Diagram Example
)
1/THROUGHPUT
TRACK-AND-HOLD IN HOLD
13
Timing Example 2
The
As shown in Figure 3, assuming V
throughput of 50 kSPS gives a cycle time of t
20 μs. With t
and t
satisfies the requirement of 10 ns for t
powered up and the signal is fully acquired at Point A, which
means the acquisition/power-up time is t
1 μs = 1.05 μs, satisfying the maximum requirement of 640 ns
for the power-up time. In this example and with other slower
clock values, the part is fully powered up and the signal already
acquired before the third SCLK falling edge; however, the track-
and-hold does not go into hold mode until that point. In this
example, the part can be powered up and the signal can be fully
acquired at approximately Point B in Figure 3.
AD7466-KGD
8
14
= 60 ns maximum, this leaves t
CONVERT
15
t
8
can also operate with slower clock frequencies.
= t
16
2
+ 15(1/f
POWER-DOWN
AUTOMATIC
SCLK
DD
t
= 1.8 V, f
QUIET
) = 55 ns + 7.5 μs = 7.55 μs,
QUIET
QUIET
Known Good Die
2
CONVERT
to be 12.39 μs, which
. The part is fully
+ 2(1/f
SCLK
= 2 MHz, and a
+ t
SCLK
8
+ t
) = 55 ns +
QUIET
=