ad7568bp-reel Analog Devices, Inc., ad7568bp-reel Datasheet - Page 3

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ad7568bp-reel

Manufacturer Part Number
ad7568bp-reel
Description
Lc2mos Octal 12-bit Dac
Manufacturer
Analog Devices, Inc.
Datasheet
REV. B
TIMING SPECIFICATIONS
Parameter
t
t
t
t
t
t
t
t
t
NOTES
1
2
Sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
t
1
2
3
4
5
6
7
8
9
8
2
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Figure 2. Load Circuit for Digital Output
Timing Specifications
TO OUTPUT
PIN
50pF
C
L
Limit at
T
100
40
40
30
30
5
90
70
40
A
= +25 C
LDAC, CLR
SDOUT (O)
CLKIN (I)
1.6mA
200 A
FSIN (I)
SDIN (I)
NOTES
1. AO IS HARDWIRED HIGH OR LOW.
I
I
OL
OH
t
4
(V
t
6
DD
DB15
Limit at
T
100
40
40
30
30
5
90
70
40
= +5 V
A
= –40 C to +85 C
+2.1V
t
5
t
2
Figure 1. Timing Diagram
5%; I
OUT1
= I
t
t
t
1
7
8
OUT2
–3–
DB0
t
9
= 0 V; T
t
Model
AD7568BS
AD7568BP
*S = Plastic Quad Flatpack (PQFP), P = Plastic Leaded Chip Carrier (PLCC).
DB15
3
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
A
= T
MIN
to T
Temperature
Range
–40 C to +85 C
–40 C to +85 C
MAX
, unless otherwise noted)
Description
CLKIN Cycle Time
CLKIN High Time
CLKIN Low Time
FSIN Setup Time
Data Setup Time
Data Hold Time
FSIN Hold Time
SDOUT Valid After CLKIN Falling Edge
LDAC, CLR Pulse Width
ORDERING GUIDE
DB0
Linearity
Error (LSBs)
0.5
0.5
AD7568
Package
Option*
S-44
P-44A

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