ad7868bq Analog Devices, Inc., ad7868bq Datasheet - Page 5

• Manufacturer Part Number: ad7868bq
• Description: Lc2mos Complete, 12-bit Analog I/o System
• Manufacturer: Analog Devices, Inc.

PIN FUNCTION DESCRIPTION
DIP Pin
Number
POWER SUPPLY
7 & 23
10 & 22
8 & 19
6 &17
ANALOG SIGNAL AND REFERENCE
21
9
20
11
12
ADC INTERFACE AND CONTROL
2
3
4
5
1
24
DAC INTERFACE AND CONTROL
14
15
16
13
18
REV. B
V
Mnemonic
V
V
AGND
DGND
V
RO ADC
RO DAC
RI DAC
CLK
RFS
RCLK
DR
CONVST
CONTROL
TFS
DT
TCLK
LDAC
NC
DD
SS
IN
OUT
Function
Positive Power Supply, 5 V
Negative Power Supply, –5 V
Analog Ground. Both AGND pins must be tied together.
Digital Ground. Both DGND pins must be tied together.
ADC Analog Input. The ADC input range is 3 V.
Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is
bipolar, 3 V with RI DAC = +3 V.
Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be
used as a reference for the DAC by connecting it to the RI DAC input. The external load capability of
this reference is 500 A.
DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC
with this internal reference, RO DAC should be connected to RI DAC. The external load capability of
the reference is 500 A.
DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is
internally buffered before being applied to the DAC. The nominal reference voltage for correct
operation of the AD7868 is 3 V.
Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying pin to
V
Receive Frame Synchronization, Logic Output. This is an active low open-drain output which provides
a framing pulse for serial data. An external 4.7 k pull-up resistor is required on RFS.
Receive Clock, Logic Output. RCLK is the gated serial clock output which is derived from the internal
or external ADC clock. If the CONTROL input is at V
CONTROL input at DGND the RCLK output is gated off (three-stated) after serial transmission is
complete. RCLK is an open-drain output and requires an external 2 k pull-up resistor.
Receive Data, Logic Output. This is an open-drain data output used in conjunction with RFS and
RCLK to transmit data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is
low. An external 4.7 k resistor is required on the DR output.
Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into
the hold mode and starts an ADC conversion. This input in asynchronous to the CLK input.
Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the
RCLK is continuous. Note, tying this pin to V
operation is not exhibited.
Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC
with serial data expected after the falling edge of this signal.
Transmit Data, Logic Input. This is the data input which is used in conjunction with TFS and TCLK
to transfer serial data to the input latch.
Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when TFS is low.
Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the
falling edge of this signal.
No Connect.
SS
enables the internal laser-trimmed oscillator.
5%. Both V
5%. Both V
–5–
DD
SS
pins must be tied together.
pins must be tied together.
DD
places the part in a factory test mode where normal
SS
the clock runs continuously. With the
AD7868