pi6cv855 Pericom Semiconductor Corporation, pi6cv855 Datasheet

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... FBOUT). The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the Analog Power input (AV DD PLL is turned off and bypassed for test purposes. The PI6CV855 is able to track Spread Spectrum Clocking to reduce EMI. Pin Configuration GND Y0 ...

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... PI6CV855 ...

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... – – ± PI6CV855 μ PS8545D 02/12/08 ...

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... – ± PS8545D PI6CV855 ° μ 02/12/08 ...

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... – – PI6CV855 ...

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... DDQ /2 V DDQ /2 08-0030 Z = 60W R =120W Z = 60W Figure 1. IBIS Model Output Load C=14pF V DDQ /2 C=14pF V DDQ /2 Figure 2. Output Load Test Circuit 6 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory DDR SDRAM DDR SDRAM SCOPE PS8545D 02/12/08 ...

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... Yx, FBOUT Yx, FBOUT 08-0030 t t cycle n cycle n jit(cc) cycle n cycle n+1 Figure 3. Cycle-to-Cycle Jitter ∑ large number of samples) Figure 4. Static Phase Offset t sk(o) Figure 5. Output Skew 7 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory t n PS8545D 02/12/08 ...

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... Figure 6. Period Jitter t half period n half period jit(hper) half period n 2*f Figure 7. Half-Period Jitter sl(i), sl(o) sl(i), sl(o) Figure 8. Input and Output Slew Rates 8 PI6CV855 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory n DDQ 80% 20% 0V PS8545D 02/12/08 ...

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... DESCRIPTION: 28-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L Package Code L Pb-free & Green, 28-pin 173-mil wide TSSOP 9 PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory DOCUMENT CONTROL NO 1313 REVISION: D DATE: 03/09/05 .004 0.09 0.20 .008 0.45 .018 0.75 .030 .252 BSC 6.4 Package Type PI6CV855 PS8545D 02/12/08 ...