MC74HCT374AFELG ON Semiconductor, MC74HCT374AFELG Datasheet

no-image

MC74HCT374AFELG

Manufacturer Part Number
MC74HCT374AFELG
Description
IC FLIP FLOP OCT D 3ST 20-SOEIAJ
Manufacturer
ON Semiconductor
Series
74HCTr
Type
D-Type Busr
Datasheet

Specifications of MC74HCT374AFELG

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
30MHz
Delay Time - Propagation
31ns
Trigger Type
Positive Edge
Current - Output High, Low
6mA, 6mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MC74HCT374A
Octal 3−State Noninverting
D Flip−Flop with
LSTTL−Compatible Inputs
High−Performance Silicon−Gate CMOS
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
the rising edge of Clock. The Output Enable does not affect the state of
the flip−flops, but when Output Enable is high, the outputs are forced
to the high−impedance state. Thus, data may be stored even when the
outputs are not enabled.
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT534A, which has
inverting outputs.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2005
June, 2005 − Rev. 10
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC74HCT374A may be used as a level converter for
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with
The HCT374A is identical in function to the HCT574A, which has
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 276 FETs or 69 Equivalent Gates
Improvements over HCT374
Pb−Free Packages are Available*
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
1
20
20
20
20
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
1
1
1
A
L, WL
Y, YY
W, WW
G
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
http://onsemi.com
DW SUFFIX
CASE 751D
CASE 948E
SOEIAJ−20
DT SUFFIX
SOICW−20
TSSOP−20
CASE 738
CASE 967
N SUFFIX
F SUFFIX
PDIP−20
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Pb−Free Package
Publication Order Number:
20
20
20
1
1
1
MC74HCT374AN
20
MC74HCT374A/D
DIAGRAMS
1
MARKING
AWLYYWWG
AWLYYWWG
AWLYYWWG
74HCT374A
ALYWG
HCT374A
374A
HCT
G

Related parts for MC74HCT374AFELG

MC74HCT374AFELG Summary of contents

Page 1

... Improved Input Noise and Latchup Immunity • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 June, 2005 − Rev. 10 http://onsemi.com PDIP− ...

Page 2

... NAND gate. ORDERING INFORMATION Device MC74HCT374AN MC74HCT374ANG MC74HCT374ADW MC74HCT374ADWG MC74HCT374ADWR2 MC74HCT374ADWR2G MC74HCT374ADTR2 MC74HCT374ADTR2G MC74HCT374AFEL MC74HCT374AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. MC74HCT374A ...

Page 3

... Total Supply Current = I Î Î Î Î Î Î Î Î Î Î Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D) MC74HCT374A Î Î Î Î Î Î Î Î Value Unit Î ...

Page 4

... For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D) C Power Dissipation Capacitance (Per Flip−Flop Used to determine the no−load dynamic power consumption Semiconductor High−Speed CMOS Data Book (DL129/D). = 5.0 V ± 10%, Input t TIMING REQUIREMENTS (V CC Î Î Î Î ...

Page 5

V CLOCK 1 1/f max t t PLH PHL 90 TLH THL Figure 1. TEST POINT OUTPUT DEVICE UNDER C TEST L *Includes all ...

Page 6

SEATING PLANE 0.25 (0.010 20X 0. 18X A1 MC74HCT374A PACKAGE DIMENSIONS PDIP−20 N SUFFIX CASE ...

Page 7

K 20X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT 1 0.15 (0.006 −V− 0.100 (0.004) −T− SEATING PLANE MC74HCT374A TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE ...

Page 8

... E L DETAIL P VIEW American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982 ...

Related keywords