scan25100-evk National Semiconductor Corporation, scan25100-evk Datasheet - Page 9

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scan25100-evk

Manufacturer Part Number
scan25100-evk
Description
2457.6, 1228.8, And 614.4 Mbps Cpri Serdes With Auto Re Sync And Precision Delay Calibration Measurement
Manufacturer
National Semiconductor Corporation
Datasheet
R
RLR
t
JIT
F
t
TRANSMITTER INPUT TIMING SPECIFICATIONS
t
t
t
f
RECEIVER OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1, 1228.8 and 614.4 Mbps only)
t
t
f
t
RECEIVER OUTPUT TIMING SPECIFICATIONS (Write Mode RXCLKMODE=0)
t
t
t
f
t
CDET OUTPUT TIMING SPECIFICATIONS (Read Mode RXCLKMODE=1, 1228.8 and 614.4 Mbps only)
t
CDET OUTPUT TIMING SPECIFICATIONS (Write Mode RXCLKMODE=0) (Note 5)
t
t
SYSCLK LVDS OUTPUT TIMING SPECIFICATIONS
t
JIT
t
MDC/MDIO TIMING SPECIFICATIONS (Clause 45)
f
LAT-R
R-LOCK
S-T
H-T
DC
TXCLK
PDRX
DC
RXCLKR
R
S-R
H-R
DC
RXCLK
R
PDCD
S-C
H-C
SYSCLKNDC
R
MDC
R-LOCK
R
, t
, t
, t
Symbol
R-TOL
SYSCLK
F
F
F
I
Differential Input Terminations
Input Return Loss (Note 12)
Receive latency
(Notes 10, 8)
Total input jitter tolerance (Note 12) Input CJPAT with BER of 10
Receiver lock range
Maximum lock time
Setup Time
Hold Time
Duty cycle
TXCLK frequency
RXCLK Propagation Delay
Duty cycle
RXCLK input frequency
Output data transition time
Setup Time
Hold Time
Duty cycle
RXCLK frequency
Output data transition time
CDET Propagation Delay
Setup Time
Hold Time
Duty cycle
Cycle to cycle jitter
Output transition time
MDC Frequency
Parameter
Frequency = 1.229 GHz
614.4 Mbps
1.228 Gbps
2.4576 Gbps
(Note 4)
Input data rate reference to local
transmit data rate.
K28.5 pattern at 2457.6 Mbps
DIN [9:0] valid to TXCLK rising or
falling edge
TXCLK rising or falling edge to DIN
[9:0] valid
TXCLK duty cycle
RXCLK rising or falling edge to
ROUT [9:0] valid
RXCLK input duty cycle
RXCLK input frequency
For ROUT [0-9], LOCK, etc. pins.
Measured between 20% and 80%
levels
ROUT [9:0] valid to RXCLK rising or
falling edge (Note 11)
RXCLK rising or falling edge to
ROUT [9:0] valid (Note 11)
RXCLK duty cycle
For ROUT [0-9], LOCK, etc. pins.
Measured between 20% and 80%
levels
RXCLK rising or falling edge to
CDET
CDET valid to RXCLK rising or
falling edge
RXCLK rising or falling edge to
CDET valid
(Note 12)
Between 20% and 80% levels (Note
12)
Condition
9
−12
−200
Min
0.5
0.5
0.9
0.9
1.1
0.1
80
45
30
45
30
45
30
40
2
2
1
0
(Note 2)
0.35
0.35
Typ
100
280
140
-20
1.5
1.5
75
40
4
4
+200
Max
0.66
62.5
120
125
125
-15
0.3
2.5
55
55
55
60
65
1
6
6
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ps p-p
Units
UIp-p
MHz
MHz
MHz
MHz
ppm
ms
dB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%

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