scan921025h05 National Semiconductor Corporation, scan921025h05 Datasheet - Page 20

• Manufacturer Part Number: scan921025h05
• Description: High Temperature 20-80 Lvds Serdes With Ieee 1149.1 Jtag At-speed Bist
• Manufacturer: National Semiconductor Corporation

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ROUT
RCLKR/F
RI+
RI−
PWRDN
LOCK
RCLK
REN
DVCC
DGND
AVCC
AGND
REFCLK
TDI
TDO
TMS
TCK
TRST
N/C
Deserializer Pin Descriptions
Deserializer Truth Table
1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F.
3) ROUT and RCLK are TRI-STATED when LOCK is asserted High.
4) During Power-up.
Pin Name
PWRDN
H (4)
H
H
L
INPUTS
N/A
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
REN
H
H
X
L
F5, F7, G4, G5
A2, C3, D4, E3
C4, C7, D6,
A7, B7, C5,
D7, E4, E7,
A5, B4, B6,
A1, A6, B5,
B1, C2, F1,
A4, B2, F3,
Ball Id.
C6, D5
F2, G1
F4, G2
D2
C1
D3
D1
G3
G6
G7
B3
E1
E2
A3
F6
E5
E6
ROUT [0:9]
Data Output.
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High selects
rising edge. Low selects falling edge.
+ Serial Data Input. Non-inverting Bus LVDS differential input.
− Serial Data Input. Inverting Bus LVDS differential input.
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wired OR connections.
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. When driven low, TRI-STATEs
ROUT0–ROUT9 and RCLK.
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
Test Data Input to support IEEE 1149.1. There is an internal pullup
resistor that defaults this input to high per IEEE 1149.1.
Test Data Output to support IEEE 1149.1
Test Mode Select Input to support IEEE 1149.1. There is an
internal pullup resistor that defaults this input to high per IEEE
1149.1.
Test Clock Input to support IEEE 1149.1
Test Reset Input to support IEEE 1149.1. There is an internal
pullup resistor that defaults this input to high per IEEE 1149.1.
Leave open circuit, do not connect
Active
20
Z
Z
Z
±
9 mA CMOS level outputs.
OUTPUTS
Description
LOCK
Active
H
L
Z
Active
RCLK
Z
Z
Z