fs6377 AMI Semiconductor, Inc., fs6377 Datasheet - Page 23

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fs6377

Manufacturer Part Number
fs6377
Description
Fs6377-01g Programmable 3-pll Clock Generator Ic
Manufacturer
AMI Semiconductor, Inc.
Datasheet

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FS6377-01x Programmable 3-PLL Clock Generator IC
Next, click on the PLL A box. A pop-up screen similar to Figure 15 should appear. Type in a desired output clock frequency in MHz, set
the operating voltage (3.3V or 5V) and the desired maximum output frequency error. Pressing Calculate Solutions generates several
possible divider and VCO-speed combinations.
For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as
small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a post divider of two to obtain an
optimal 50 percent duty cycle.
Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv
value in Solution #7 into post divider A and switches mux A to take the output of PLL A.
The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that
mux A has been switched to PLL A and the post divider A has the chosen 100MHz output displayed.
Repeat the steps for PLL B.
PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C and mux D are also affected
by the logic level on the SEL_CD pin, as are the post dividers C and D.
AMI Semiconductor
www.amis.com
Specifications subject to change without notice
– Oct., 2007 – Rev. 3.0
Figure 16: Post Divider Menu
Figure 15: PLL Screen
23
Data Sheet

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