fs6370 AMI Semiconductor, Inc., fs6370 Datasheet - Page 6

• Manufacturer Part Number: fs6370
• Description: Fs6370-01g Eeprom Programmable 3-pll Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

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F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 / / F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 g g E E E E P P R R O O M M P P r r o o g g r r a a m m m m a a b b l l e e 3 3 - - P P L L L L C C l l o o c c k k G G e e n n e e r r a a t t o o r r I I C C
A A M M I I S S e e m m i i c c o o n n d d u u c c t t o o r r - - R R e e v v . . 2 2 . . 0 0 , , M M a a r r . . 0 0 5 5
4 4 . . 3 3 O O s s c c i i l l l l a a t t o o r r O O v v e e r r d d r r i i v v e e
For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be connected to XOUT
and XIN must be left unconnected (float).
For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times, and can swing rail-to-
rail.
If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01µF or 0.1µF capacitor. A minimum 1V peak-to-
peak signal is required to drive the internal differential oscillator buffer.
5.0 Run Mode
If the MODE pin is set to a logic-high, the device enters the run mode. The high state is latched (see MODE pin). The FS6370 then copies the stored
EEPROM data into its control registers and begins normal operation based on that data when the self-load is complete.
The self-load process takes about 89,000 clocks of the crystal oscillator. During the self-load time, all clock outputs are held low. At a reference frequency
of 27MHz, the self-load takes about 3.3ms to complete.
If the EEPROM is empty (all zeros), the crystal reference frequency provides the clock for all four outputs.
No external programming access to the FS6370 is possible in run mode. The dual-function PD/SCL and OE/SDA pins become a power-down (PD) and
output enable (OE) control, respectively.
5 5 . . 1 1 P P o o w w e e r r - - D D o o w w n n a a n n d d O O u u t t p p u u t t E E n n a a b b l l e e
A logic-high on the PD/SCL pin powers down only those portions of the FS6370 which have their respective power-down control bits enabled. Note that
the PD/SCL pin has an internal pull-up.
When a post divider is powered down, the associated output driver is forced low. When all PLLs and post dividers are powered down the crystal oscillator
is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high.
A logic-low on the OE/SDA pin tristates all output clocks. Note that this pin has an internal pull-up.
6.0 Program Mode
If the MODE pin is logic-low, the device enters the program mode. All internal registers are cleared to zero, delivering the crystal frequency to all outputs.
The device allows programming of either the internal 128-bit EEPROM or the on-chip control registers via I
The EEPROM and the FS6370 act as two separate parallel devices on the same on-chip I
is done via the I
The dual-function PD/SCL and OE/SDA pins become the serial data I/O (SDA) and serial clock input (SCL) for normal I
down and output enable control via the PD/SCL and OE/SDA pins is not available.
6 6 . . 1 1 E E E E P P R R O O M M P P r r o o g g r r a a m m m m i i n n g g
Data must be loaded into the EEPROM in a most-significant-bit (MSB) to least-significant-bit (LSB) order. The register map of the EEPROM is noted in
Table 3.
The device address of the EEPROM is:
A A 6 6
1
2
C device address.
A A 5 5
0
A A 4 4
1
A A 3 3
0
A A 2 2
X
A A 1 1
X
6
A A 0 0
X
2
C-bus. Choosing either the EEPROM or the device control registers
2
C control over the PD/SCL and OE/SDA pins.
2
C communications. Note that power-
Data Sheet