s29al008d Meet Spansion Inc., s29al008d Datasheet - Page 27

• Manufacturer Part Number: s29al008d
• Description: 8 Megabit 1 M X 8-bit/512 K X 16-bit Cmos 3.0 Volt-only Boot Sector Flash Memory
• Manufacturer: Meet Spansion Inc.

9. Write Operation Status
9.1
November 27, 2007 S29AL008D_00_A10
DQ7: Data# Polling
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#.
RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or
in progress. These three bits are discussed first.
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7.
This is analogous to the complement/true datum output described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The
system must provide an address within any of the sectors selected for erasure to read valid status information
on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
When the system detects DQ7 changes from the complement to true data, it can read valid data at DQ7–DQ0
on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output
Enable (OE#) is asserted low.
on page
Table 9.1 on page 31
Polling algorithm.
41, illustrates this.
Table 9.1 on page 31
shows the outputs for Data# Polling on DQ7.
D a t a
Figure 15.8, Data# Polling Timings (During Embedded Algorithms)
S h e e t
and the following subsections describe the functions of these bits. DQ7,
S29AL008D
Figure 9.1 on page 28
shows the Data#
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