nt1gc64bh4b0ps Nanya Techology, nt1gc64bh4b0ps Datasheet - Page 19

• Manufacturer Part Number: nt1gc64bh4b0ps
• Description: Unbuffered Ddr3 So-dimm
• Manufacturer: Nanya Techology

NT1GC64BH4B0PS / NT2GC64B88B0NS / NT4GC64B8HB0NS
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600
Unbuffered DDR3 SO-DIMM
AC Timing Specifications for DDR3 SDRAM Devices Used on Module
REV 0.1
01/2010
Clock Timing
tCK(DLL_OF Minimum Clock Cycle Time (DLL off mode)
tCK(avg)
tCH(avg)
tCL(avg)
tCK(abs)
tCH(abs)
tCL(abs)
JIT(per)
tJIT(per,lck)
tJIT(cc)
tJIT(cc,lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per) Cumulative error accross 10 cycles
tERR(11per) Cumulative error accross 11 cycles
tERR(12per) Cumulative error accross 12 cycles
tERR(nper)
Data Timing
tDQSQ
tQH
tLZ(DQ)
tHZ(DQ)
tDS(base)
AC175
tDS(base)
AC150
tDH(base)
DC100
tDIPW
Data Strobe Timing
tRPRE
tRPST
tQSH
tQSL
tWPRE
tWPST
tDQSCK
tLZ(DQS)
tHZ(DQS)
tDQSL
tDQSH
tDQSS
tDSS
tDSH
Symbol
Average Clock Period(Refer to "Standard Speed
Average high pulse width
Average low pulse width
Absolute Clock Period
Absolute high pulse width
Absolute low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Clcyle Period Jitter
Cycle to Cycle Period Jitter
Cumulative error accross 2 cycles
Cumulative error accross 3 cycles
Cumulative error accross 4cycles
Cumulative error accross 5cycles
Cumulative error accross 6 cycles
Cumulative error accross 7 cycles
Cumulative error accross 8 cycles
Cumulative error accross 9 cycles
Cumulative error accross n=13,14,..,49,50 cycles
DQS, DQS to DQ skew per group, per access
DQ output hold time from DQS, DQS
DQ low-impedence time from CK / 
DQ high-impedence time from CK / 
Data Setup time to DQS, DQS referenced to
Vih(ac)/ Vil(ac) levels
Data Setup time to DQS, DQS referenced to
Vih(ac)/ Vil(ac) levels
Data Hold time to DQS, DQS referenced to Vih(dc)/
Vil(dc) levels
DQ and DM Input pulse width for each input
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
DQS, DQS rising edge output access time from
rising CK, 
DQS, DQS low-impedance time (Referenced from
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK,  rising edge
DQS, DQS falling edge setup time to CK,  rising
edge
DQS, DQS falling edge hold time to CK,  rising
Parameter
tERR(npr)min =
(1+ 0.68In(n)) *
tCK(avg)min +
tJIT(per)min
tJIT(per)min
19
-0.25
0.47
0.47
0.43
0.43
-132
-157
-175
-188
-200
-209
-217
-224
-231
-237
-242
0.38
-600
0.38
0.38
-300
-600
0.45
0.45
min
100
490
-90
-80
0.9
0.3
0.9
0.3
0.2
0.2
25
75
8
DDR3-1066 (-BE)
-
-
-
180
160
tERR(npr)max =
tCK(avg)max +
(1+ 0.68In(n)) *
tJIT(per)max
tJIT(per)max
NANYA reserves the right to change products and specifications without notice.
Note 19
Note 11
max
0.53
0.53
0.55
0.55
0.25
132
157
175
188
200
209
217
224
231
237
242
150
300
300
300
300
300
90
80
-
-
-
-
-
-
-
-
-
-
tCK(avg)min +
tERR(npr)min
tJIT(per)min
tJIT(per)min
0.68In(n)) *
= (1+
-0.25
0.47
0.47
0.43
0.43
-118
-140
-155
-168
-177
-186
-193
-200
-205
-210
-215
0.38
-500
-255
-500
0.45
0.45
min
400
-80
-70
0.9
0.3
0.4
0.4
0.9
0.3
0.2
0.2
30
65
DDR3-1333 (-CG)
8
-
-
-
-
© NANYA TECHNOLOGY CORPORATION
160
140
tCK(avg)max +
tERR(npr)max
tJIT(per)max
tJIT(per)max
0.68In(n)) *
Note 19
Note 11
= (1+
max
0.53
0.53
0.55
0.55
0.25
118
140
155
168
177
186
193
200
205
210
215
125
250
250
255
250
250
80
70
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Unit
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps