nt1gt72u4pb0bv Nanya Techology, nt1gt72u4pb0bv Datasheet - Page 18

• Manufacturer Part Number: nt1gt72u4pb0bv
• Description: 240pin Registered Ddr2 Sdram Module Based On 64mx8 & 128mx4 Ddr2 Sdram Die B
• Manufacturer: Nanya Techology

NT2GT72U4NB0BV / NT2GT72U4NB1BV
NT512T72U89B0BV / NT1GT72U4PB0BV
512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72
Registered DDR2 SDRAM DIMM
Operating, Standby, and Refresh Currents
(T
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.
REV 1.3
05/2007
Symbol
I
I
I
I
I
I
I
I
CASE
I
I
I
I
I
DD3PF
DD3PS
DD4W
DD2N
DD2Q
DD3N
DD4R
DD2P
DD0
DD1
DD5
DD6
DD7
= 0 ° C ~ 85 ° C; V
Operating Current: one bank; active/precharge; t
(MIN);
and control inputs changing once per clock cycle
Operating Current: one bank; active/read/precharge; Burst = 2; t
(MIN);
changing once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE ≤ V
Idle Standby Current: CS ≥ V
t
Precharge quiet standby current; All banks idle; t
HIGH;
Data bus inputs are FLOATING.
Active Power-Down Standby Current: one bank active; power-down
mode; CKE ≤ V
Active Power-Down Standby Current: one bank active; power-down
mode; CKE ≤ V
Active Standby Current: one bank; active/precharge; CS ≥ V
≥ V
changing twice per clock cycle; address and control inputs changing
once per clock cycle
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 2.5; t
0mA
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
inputs changing twice per clock cycle; CL=2.5; t
Auto-Refresh Current: t
Self-Refresh Current: CKE ≤ 0.2V
Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; t
CK
(MIN);
IH
(MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
CL=2.5; t
address and control inputs changing once per clock cycle
RC
is HIGH; Other control and address bus inputs are STABLE;
t
RC
= t
= t
DDQ
RC
CK
IL
IL
IL
RAS
(min); I
= t
(MAX);
(MAX);
(MAX);
= 1.8V ± 0.1V (2GB, 2 Rank, 64Mx8 DDR2 SDRAMs)
CK
(MAX)
(MIN);
RC
t
t
t
CK
CK
CK
OUT
; t
= t
Parameter/Condition
= t
= t
= t
CK
= 0mA.
I
RFC
OUT
IH
CK
CK
CK
= t
(MIN);
(MIN)
(MIN); Fast PDN Exit MRS(12) = 0mA
(MIN); Slow PDN Exit MRS(12) = 1mA
(MIN)
CK
= 0mA; address and control inputs
(MIN)
all banks idle; CKE ≥ V
; DQ, DM, and DQS inputs
CK
RC
CK
= t
CK
=t
= t
CK
= t
CK
RC
(IDD); CKE is
CK
(MIN)
(MIN);
18
(MIN);
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
IH
IH
(MIN)
t
(MIN);
CK
I
RC
OUT
= t
; t
= t
=
CK
CKE
CK
RC
=
PC2-5300
(-3C)
2816
3113
2321
1925
1648
2321
4015
4015
4411
4697
619
698
278
PC2-6400
(-25D)
3212
3509
2321
2361
1885
2717
4312
4411
5203
5390
619
698
278
PC2-6400
© NANYA TECHNOLOGY CORP.
(-25C)
3212
3509
2321
2361
1885
2717
4312
4411
5203
5390
619
698
278
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA