nt1gt72u8pb0by Nanya Techology, nt1gt72u8pb0by Datasheet - Page 7
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nt1gt72u8pb0by
Manufacturer Part Number
nt1gt72u8pb0by
Description
240pin Unbuffered Ddr2 Sdram Module With Ecc Based On 64mx8 Ddr2 Sdram B Die
Manufacturer
Nanya Techology
Datasheet
1.NT1GT72U8PB0BY.pdf
(21 pages)
NT512T72U89B0BY / NT1GT72U8PB0BY
512MB: 64M x 72 / 1GB: 128M x 72
Unbuffered DDR2 SDRAM DIMM with ECC
Serial Presence Detect –
64Mx72 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
REV 1.3
03/2007
Byte
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
0
1
2
3
4
5
6
7
8
9
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank, Package, and Height
Data Width of this Assembly
Reserved
Voltage Interface Level of this Assembly
DDR2 SDRAM Cycle Time at CL=5
DDR2 SDRAM Access Time from Clock at CL=5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR2 SDRAM Width
Error Checking DDR2 SDRAM Device Width
Reserved
DDR2 SDRAM Device Attributes: Burst Length Supported
DDR2 SDRAM Device Attributes: Number of Device Banks
DDR2 SDRAM Device Attributes:
Reserved
DDR2 SDRAM DIMM Type Information
DDR2 SDRAM Module Attributes:
DDR2 SDRAM Device Attributes: General
Minimum Clock Cycle at CL=4
Maximum Data Access Time (t
Minimum Clock Cycle Time at CL=3
Maximum Data Access Time (t
Minimum Row Precharge Time (t
Minimum Row Active to Row Active delay (t
Minimum RAS to CAS delay (t
Minimum RAS Pulse Width (t
Module Bank Density
Address and Command Setup Time Before Clock (t
Address and Command Hold Time After Clock (t
Data Input Setup Time Before Clock (t
Data Input Hold Time After Clock (t
Write Recovery Time (t
WR
Description
)
RAS
Part 1 of 3 (512MB)
RCD
ac
ac
)
) from Clock at CL=4
) from Clock at CL=3
RP
)
)
DH
)
DS
Latencies Supported
)
RRD
)
IH
)
IS
)
7
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
±0.50
Regular UDIMM (133.35mm)
0.375
0.225
-37B
3.75
0.25
ns
ns
ns
ns
ns
0.10ns
1 rank, Height=30mm
Support weak Driver,
50: ODT, and PASR
15.0
15.0
SPD Entry Value
ns
ns
3.75ns
Normal DIMM
±0.45
0.275
0.175
3,4,5
±0.5
±0.6
0.20
-3C
SSTL_1.8V
5.0
Undefined
ns
ns
Undefined
ns
ns
ns
ns
ns
ns
7.89s/self
3
<4.1mm
512MB
15.0ns
DDR2
7.5ns
ECC
45.0
128
256
4,8
X8
X8
14
10
72
4
±0.40
-25C
12.5
12.5
2.5
ns
ns
ns
ns
0.175ns
0.125ns
0.25ns
0.05ns
±0.40
±0.45
3.0ns
-25D
4,5,6
15ns
3.75
±0.5
2.5
ns
ns
ns
ns
ns
15
ns
-37B
3D
50
25
37
22
Serial PD Data Entry
3C
3C
10
(Hexadecimal)
-3C
3D
© NANYA TECHNOLOGY CORP.
30
45
38
50
50
60
20
27
17
0E
0A
0C
1E
2D
3C
80
08
08
60
48
00
05
02
82
08
08
00
04
01
02
00
07
80
-25C
25
40
32
32
17
25
05
12
-25D
3D
3C
3C
25
40
70
30
45
50
Note