nt1gt72u8pa1by Nanya Techology, nt1gt72u8pa1by Datasheet - Page 13

• Manufacturer Part Number: nt1gt72u8pa1by
• Description: 240pin Unbuffered Ddr2 Sdram Module With Ecc
• Manufacturer: Nanya Techology

NT512T72U89A1BY / NT1GT72U8PA1BY
512MB: 64M x 72 / 1GB: 128M x 72
Unbuffered DDR2 SDRAM DIMM with ECC
Operating, Standby, and Refresh Currents
T
Note:
REV 1.3
08/2006
Symbol
I
I
CASE
I
I
I
I
I
I
I
I
DD3PS
I
I
I
DD3PF
DD4W
DD2Q
DD2P
DD2N
DD3N
DD4R
DD0
DD1
DD5
DD6
DD7
1.
= 0 ° C ~ 85 °C; V
Module IDD was calculated from component IDD. It may differ from the actual measurement.
Operating Current: one bank; active/precharge; t
(MIN);
and control inputs changing once per clock cycle
Operating Current: one bank; active/read/precharge; Burst = 2; t
(MIN);
changing once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE ≤ V
Idle Standby Current: CS ≥ V
t
Precharge Quiet Standby Current: All banks idle;
HIGH; t
inputs are floating.
Active Power-Down Current: All banks open; t
Other control and address inputs are STABLE, Data bus inputs are
floating. MRS A12 bit is set to low (Fast Power-down Exit).
Active Power-Down Current: All banks open; t
Other control and address inputs are STABLE, Data bus inputs are
floating. MRS A12 bit is set to high (Slow Power-down Exit).
Active Standby Current: one bank; active/precharge; CS ≥ V
V
changing twice per clock cycle; address and control inputs changing once
per clock cycle
Operating Current: one bank; Burst = 2; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 2.5; t
Operating Current: one bank; Burst = 2; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL=2.5; t
Auto-Refresh Current: t
Self-Refresh Current: CKE ≤ 0.2V
Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; t
CK (MIN);
IH (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
CL=2.5; t
CK
address and control inputs changing once per clock cycle
t
RC
= t
RC
= t
DDQ
CK (MIN)
= t
CK
RC
IL (MAX);
RAS (MAX)
= V
= t
(min); I
; Other control and address inputs are stable, Data bus
DD
CK (MIN);
= 1.8V ± 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs)
RC
t
CK
; t
OUT
= t
Parameter/Condition
CK
= t
IH (MIN);
RFC (MIN)
I
= 0mA.
OUT
CK (MIN)
= t
CK (MIN)
= 0mA; address and control inputs
all banks idle; CKE ≥ V
; DQ, DM, and DQS inputs
CK
CK
= t
= t
CK
CK
CK (MIN)
CK (MIN);
RC
= t
= t
= t
CK (MIN)
CK (MIN)
is HIGH; CKE is
RC (MIN);
I
13
OUT
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
, CKE is LOW;
, CKE is LOW;
IH (MIN)
IH (MIN);
= 0mA
t
CK
RC
= t
; t
= t
CKE ≥
CK
CK
RC
=
PC2-5300
(-3C)
1125
1260
1620
1710
1890
1980
900
720
342
108
900
90
90
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
© NANYA TECHNOLOGY CORP.
1
1
1
1
1
1
1
1
1
1
1
1
1