nt1gt64u8hb0bn-3c Nanya Techology, nt1gt64u8hb0bn-3c Datasheet - Page 18
nt1gt64u8hb0bn-3c
Manufacturer Part Number
nt1gt64u8hb0bn-3c
Description
Pc2-4200 / Pc2-5300 / Pc-6400 Unbuffered Ddr2 So-dimm
Manufacturer
Nanya Techology
Datasheet
1.NT1GT64U8HB0BN-3C.pdf
(24 pages)
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.
Symbol
IDD3PS
IDD3PF
IDD4W
IDD2P
IDD2Q Precharge quiet standby current
IDD2N
IDD3N
IDD4R
IDD5B
IDD5D
NT256T64UH4B0FN / NT512T64UH8B0FN / NT1GT64U8HB0BN
NT256T64UH4B0CN / NT512T64UH8B0CN / NT1GT64U8HB0AN
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
PC2-4200 / PC2-5300 / PC-6400 Unbuffered DDR2 SO-DIMM
Operating, Standby, and Refresh Currents
T
REV 1.2
08/2007
IDD0
IDD1
IDD6
IDD7
CASE
= 0 ° C ~ 85 °C; V
Operating Current: one bank; active/precharge; t
DQ, DM, and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
Operating Current: one bank; active/read/precharge; Burst = 4; t
(MIN)
once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE ≤ V
Idle Standby Current: CS ≥ V
(MIN)
Active Power-Down Standby Current: one bank active; power-down
mode; CKE ≤ V
Active Power-Down Standby Current: one bank active; power-down
mode; CKE ≤ V
Active Standby Current: one bank; active/precharge; CS ≥ V
V
twice per clock cycle; address and control inputs changing once per clock
cycle
Operating Current: one bank; Burst = 4; reads; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS outputs
changing twice per clock cycle; CL = 4; t
Operating Current: one bank; Burst = 4; writes; continuous burst; address
and control inputs changing once per clock cycle; DQ and DQS inputs
changing twice per clock cycle; CL= 4; t
Burst Refresh Current: t
Distributed Refresh Current: t
Self-Refresh Current: CKE ≤ 0.2V
Operating Current: four bank; four bank interleaving with BL = 4, address
and control inputs randomly changing; 50% of data changing at every
transfer; t
IH (MIN)
; CL= 4; t
; address and control inputs changing once per clock cycle
; t
RC
RC
= t
= t
CK
RAS (MAX)
RC (min)
= t
DDQ
IL (MAX)
IL (MAX)
IL (MAX)
CK (MIN)
= V
; I
; t
; t
; t
; t
OUT
DD
CK
CK
CK
CK
; I
RC
Parameter/Condition
OUT
= 1.8V
= t
= t
= t
= t
= 0mA.
= t
CK (MIN)
CK (MIN)
CK (MIN)
CK (MIN)
= 0mA; address and control inputs changing
IH (MIN)
RFC (MIN)
RFC
= t
; MRS(12)=0
; MRS(12)=1
; all banks idle; CKE ≥ V
; DQ, DM, and DQS inputs changing
0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs)
REF
CK
CK
= t
= t
CK (MIN)
CK (MIN)
RC
= t
; I
RC (MIN)
OUT
= 0mA
IH (MIN)
18
; t
IH (MIN)
CK
= t
; t
RC
; CKE ≥
CK
CK (MIN)
= t
= t
RC
CK
;
PC2-4300
NANYA reserves the right to change products and specifications without notice.
(-37B)
1082
1346
1346
1698
1786
994
123
616
704
493
158
757
158
123
PC2-5300
(-3C)
1100
1232
1628
1584
1936
1892
123
704
810
581
158
880
158
123
© NANYA TECHNOLOGY CORPORATION
PC2-6400
(-25D)
1250
1408
1056
1892
1892
2200
2024
123
792
898
686
158
158
123
PC2-6400
(-25C)
1276
1452
1056
1892
1892
2200
2024
123
792
898
686
158
158
123
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA