nt1gt64u88d0by Nanya Techology, nt1gt64u88d0by Datasheet - Page 18

• Manufacturer Part Number: nt1gt64u88d0by
• Description: 240pin Unbuffered Ddr2 Sdram Module
• Manufacturer: Nanya Techology

NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY
512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Operating, Standby, and Refresh Currents
T
REV 1.0
03/2008
CASE
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.
Symbol
= 0 °C ~ 85 °C; V
I
I
I
I
I
I
I
I
I
I
DD3PF
DD3PS
I
I
I
DD2Q
DD4W
DD2P
DD2N
DD3N
DD4R
DD0
DD1
DD5
DD6
DD7
Operating Current: one bank; active/precharge; t
(MIN);
and control inputs changing once per clock cycle
Operating Current: one bank; active/read/precharge; Burst = 2; t
(MIN);
changing once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE  V
Idle Standby Current: CS  V
= t
Precharge Quiet Standby Current: All banks idle;  is HIGH; CKE is
HIGH; t
bus inputs are floating.
Active Power-Down Current: All banks open; t
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to low (Fast Power-down Exit).
Active Power-Down Current: All banks open; t
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to high (Slow Power-down Exit).
Active Standby Current: one bank; active/precharge; CS  V
CKE  V
inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
inputs changing twice per clock cycle; CL=2.5; t
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 2.5; t
0mA
Auto-Refresh Current: t
Self-Refresh Current: CKE  0.2V
Operating Current: four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing; 50% of data changing at
every transfer; t
CK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; address
CL=2.5; t
CK
DDQ
IH (MIN);
= t
= V
address and control inputs changing once per clock cycle
CK (MIN)
DD
CK
IL (MAX);
RC
t
RC
= 1.8V ± 0.1V (2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs)
= t
; Other control and address inputs are stable, Data
= t
CK (MIN);
= t
RC
RAS (MAX)
RC
t
CK
(min); I
Parameter/Condition
= t
= t
IH (MIN);
RFC (MIN)
I
OUT
CK (MIN)
OUT
; t
= 0mA; address and control inputs
CK
= 0mA.
all banks idle; CKE  V
= t
CK (MIN)
CK
CK
CK
; DQ, DM, and DQS
RC
= t
= t
CK
= t
= t
CK (MIN)
CK (MIN)
18
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
CK (MIN)
= t
RC (MIN);
CK (MIN);
, CKE is
, CKE is
IH (MIN)
IH (MIN);
t
CK
RC
I
OUT
= t
= t
; t
CK
CK
=
RC
PC2-5300
(-3C)
1373
1294
1109
1417
1566
2429
2587
141
774
528
229
986
158
PC2-6400
(-AD)
1549
1443
1250
1074
1549
1734
2517
2983
141
845
546
229
158
© NANYA TECHNOLOGY CORP.
PC2-6400
(-AC)
1549
1443
1250
1074
1549
1734
2517
2983
141
845
546
229
158
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA