nt1gt64u8hb0by Nanya Techology, nt1gt64u8hb0by Datasheet - Page 4

• Manufacturer Part Number: nt1gt64u8hb0by
• Description: 256mb 32m X 64 / 512mb 64m X 64 / 1gb 128m X 64 Unbuffered Ddr2 Sdram Dimm
  
  
  
• Manufacturer: Nanya Techology

NT256T64UH4B0FY / NT512T64U88B0BY / NT1GT64U8HB0BY
256MB: 32M x 64 / 512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
Input/Output Functional Description
REV 1.2
03/2007
CK0, CK1, CK2
DQS0 – DQS8
ODT0, ODT1
CKE0, CKE1
DQ0 – DQ63
DM0 – DM8
SA0 – SA2
A11 – A13
BA0, BA1
V
A0 – A9
Symbol
A10/AP
,
V
,
DD,
V
SDA
V
SCL
DDSPD
DDQ
REF
,
–
V
,
SS
,
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Supply
Supply
Supply
Supply
Input
Input
Type
Negative
Negative
Positive
Positive
Polarity
Active
Active
Active
Active
Active
Active
Edge
Edge
Edge
High
High
High
High
Low
Low
and
-
-
-
-
-
The positive line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the
rising edge of their associated clocks.
The negative line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
When sampled at the positive rising edge of the clock,
operation to be executed by the SDRAM.
Reference voltage for SSTL-18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A14 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is
high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is
low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
Data and Check Bit Input/Output pins.
Power and ground for the DDR SDRAM input buffers and core logic
Data strobe for input and output data
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect.
Address inputs. Connected to either V
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
Serial EEPROM positive power supply.
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DD
DD
Function
or V
to act as a pull-up.
SS
DD
on the system board to configure the
to act as a pull-up.
,
© NANYA TECHNOLOGY CORP.
,
define the