ltc5587 Linear Technology Corporation, ltc5587 Datasheet - Page 17

• Manufacturer Part Number: ltc5587
• Description: Ltc5587 6 Ghz Rms Power Detector With Digital Output Features
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
The total noise at the ADC output is dominated by the
output noise of the detector, and the sampling noise
is insignificant. The peak-to-peak output noise is also
almost independent of the sample rate. Figure 13 shows
the peak-to-peak noise at the ADC output as a function
of the RF input level for a CW RF input. Increasing C
from 1000pF to 0.01μF gives roughly 2x to 3x lower noise
over input power.
Serial Interface
The LTC5587 communicates with microcontrollers, DSPs
and other external circuitry via a 3-wire interface. Figure 14
shows the operating sequence of the serial interface.
Figure 13. Peak-to-Peak Noise at ADC Output vs RF Input Power
CONV
SDO
SCK
35
30
25
20
15
10
40
5
0
–40
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
–30
RF INPUT POWER (dBm)
C
FILT
C
FILT
–20
= 0.01μF
= 1000pF
t
CONV
RECOMMENDED HIGH OR LOW
–10
f
SMPL
Hi-Z STATE
Figure 14. LTC5587 Serial Interface Timing Diagram
= 500ksps
T
0
A
= 25°C
t
1
5587 F13
10
0.3
0.225
0.15
0.075
0.6
0.525
0.45
0.375
0
SLEEP MODE
FILT
t
THROUGHPUT
t
(MSB)
2
Data Transfer
A rising CONV edge starts a conversion and disables SDO.
After the conversion, the ADC automatically goes into
sleep mode, drawing only leakage current. CONV going
low enables SDO and clocks out the MSB bit, B11. SCK
then synchronizes the data transfer with each bit being
transmitted on the falling SCK edge and can be captured
on the rising SCK edge. After completing the data transfer,
if further SCK clocks are applied with CONV low, SDO will
output zeros indefinitely (see Figure 14). For example,
16-clocks at SCK will produce the 12-bit data and four
trailing zeros on SDO.
Sleep Mode
The LTC5587 ADC enters sleep mode to save power after
each conversion if CONV remains high. In sleep mode, all
bias currents are shut down and only leakage currents
remain (about 0.1μA). The sample-and-hold is in hold
mode while the ADC is in sleep mode. The ADC returns
to sample mode after the falling edge of CONV during
power-up.
Exiting Sleep Mode and Power-Up Time
By taking CONV low, the ADC powers up and acquires an
input signal completely after the acquisition time (t
After t
by a rising edge on CONV.
B11
1
BY TAKING CONV LOW, THE DEVICE POWERS UP
AND ACQUIRES AN INPUT ACCURATELY AFTER t
t
3
2
ACQ
t
4
B10
, the ADC is ready to perform a conversion again
3
B9
t
6
t
4
5
t
ACQ
9
B3
10
B2
t
7
ACQ
11
B1
12
B0*
LTC5587
t
8
5587 F14
17
ACQ
5587f
).