ltc6802 Linear Technology Corporation, ltc6802 Datasheet
ltc6802
Available stocks
Related parts for ltc6802
ltc6802 Summary of contents
Page 1
... When multiple LTC6802-1 devices are connected in series they can operate simultaneously, permitting all cell voltages in the stack to be measured within 13ms. To minimize power, the LTC6802-1 offers a measure mode to monitor each cell for overvoltage and undervoltage conditions. A standby mode is also provided. Each cell input has an associated MOSFET switch for discharging overcharged cells ...
Page 2
... For more information on lead free part marking, go to: For more information on tape and reel specifi cations, go to: 2 PIN CONFIGURATION + + – – 1. 0.7V PART MARKING PACKAGE DESCRIPTION LTC6802IG-1 44-Lead Plastic SSOP http://www.linear.com/leadfree/ http://www.linear.com/tapeandreel/ TOP VIEW 1 CSBI CSBO 44 2 SDO SDOI 43 3 ...
Page 3
... Current into the V Pin When Idle All Serial Port Pins at Logic ‘1’ + Current into the V Pin During Serial Communications. All Serial Port Pins at Logic ‘0’ This Current is Added MODE S QS LTC6802-1 MIN TYP MAX UNITS l 1.5 mV/Bit l –0.5 0.5 mV –0.12 ...
Page 4
... LTC6802-1 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifi cations are at T SYMBOL PARAMETER Discharge Switch On-Resistance Temperature Range Thermal Shutdown Temperature Thermal Shutdown Hysteresis Voltage Mode Timing Specifi cations t Measurement Cycle Time CYCLE t SDI Valid to SCKI Rising Setup 1 t SDI Valid to SCKI Rising Hold ...
Page 5
... The V pin does not sink current. REG TOS (Pin 35): Top of Stack Input. Tie TOS to V the LTC6802-1 is the top device in a daisy chain. Tie TOS – when the LTC6802-1 is any other device in a daisy chain. When TOS is tied to V ...
Page 6
... V MODE Information section. SDI (Pin 42): Serial Data Input. The SDI pin interfaces to any logic gate (TTL levels must be driven by the SDOI pin of another LTC6802 tied to V MODE Information section. SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS ...
Page 7
... 10k – V 10Ω 30 DIE NC TEMP Δ∑ A/D CONVERTER MUX REFERENCE EXTERNAL TEMP TEMP1 TEMP2 REF LTC6802 REGULATOR 34 V REG WATCHDOG 37 TIMER WDTB 3 SCKO 2 SDOI 1 CSBO RESULTS 12 REGISTER AND 44 CSBI COMMUNICATIONS 43 SDO 42 SDI 41 SCKI ...
Page 8
... C3. For illustration these cells are labeled B3 and B4 in Figure near zero reading is encountered for B3 and B4, the MPU can command the LTC6802-1 to place 100μA current sources from the ADC inputs input C3 is open, the new reading will show zero and full-scale. Some applications may include external noise fi ...
Page 9
... Figure 1. 96-Cell Battery Stack, Daisy Chain Interface. This Application Schematic illustrates the Simplest Possible System BATTERIES #25–#84 AND LTC6802-1 LTC6802-1 ICs #3–# CSBO CSBI SDOI SDO SCKO SDI + V SCKI C12 V MODE S12 GPIO2 C11 ...
Page 10
... The voltage reading for the individual cell LTC6802-1 being measured and discharged will be valid. All discharge switches are automatically disabled during OV and UV comparison measurements. ...
Page 11
... An external resistor should be used to limit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is limited by the amount of heat that can be tolerated by the LTC6802-1. APPLICATIONS INFORMATION USING THE LTC6802-1 WITH LESS THAN 12 CELLS The LTC6802-1 can be used with as few as four cells. ...
Page 12
... By writing a GPIO confi guration register bit to a logic low, the open drain output can be activated. The GPIOs give the user the ability to turn on/off circuitry around the LTC6802-1. One example might be a circuit to verify the operation of the system. When a GPIO confi guration bit is written to a logic high, the corresponding GPIO pin may be used as an input ...
Page 13
... UV and OV conditions at the rate designated by the CDC bits. Monitor Mode The LTC6802-1 can be used as a simple monitoring circuit with no serial interface by pulling the MMB pin low. When in this mode, the interrupt status is indicated on the SDO pin using the toggle polling mode described in the Serial Port section ...
Page 14
... C9 V REG S9 V REF C8 V TEMP2 S8 V TEMP1 C7 NC − LTC6802 CSBO CSBI SDOI SDO SCKO SDI + V SCKI C12 V MODE S12 GPIO2 C11 GPIO1 S11 WDTB C10 MMB S10 TOS C9 V REG S9 V REF ...
Page 15
... Physical Layer On the LTC6802-1, seven pins comprise the low side and high side ports. The low side pins are CSBI, SCKI, SDI, and SDO. The high side pins are CSBO, SCKO and SDOI. ...
Page 16
... The other devices in the stack must have TOS tied low. See Figure 1. Data Link Layer Clock Phase And Polarity: The LTC6802-1 SPI-compat- ible interface is confi gured to operate in a system using CPHA=1 and CPOL=1. Consequently, data on SDI must be stable during the rising edge of SCKI. ...
Page 17
... The master pulls CSBI high to exit polling. Level polling: Level polling is enabled when the LVLPL bit is high. After entering a polling command, the data out line will be driven by the slave devices based on their status. When polling for the A/D converter status, data LTC6802-1 68021 F10 68021p 17 ...
Page 18
... LTC6802-1 APPLICATIONS INFORMATION out will be low when any device is busy performing an A/D conversion and will be high when no device is busy. Similarly, when polling for interrupt status, the output will be low when any device has an interrupt condition and will be high when none has an interrupt condition. ...
Page 19
... CELL10 bit=0) 0x7C (cell 12 only, if CELL10 bit=0) 0x7D (unused) 0x7E (cell self test 1; all CV=0x555) 0x7F (cell self test 2; all CV=0xAAA) LTC6802-1 68021p 19 ...
Page 20
... LTC6802-1 APPLICATIONS INFORMATION Memory Map Table 7 through Table 12 show the memory map for the LTC6802-1. Table 12 gives bit descriptions. Table 7. Confi guration (CFG) Register Group REGISTER RD/WR BIT 7 CFGR0 RD/WR WDTEN CFGR1 RD/WR DCC8 CFGR2 RD/WR MC4I CFGR3 RD/WR MC12I CFGR4 RD/WR VUV[7] CFGR5 RD/WR VOV[7] Table 8. Cell Voltage (CV) Register Group ...
Page 21
... ETMP1[6] ETMP1[5] ETMP1[4] ETMP2[2] ETMP2[1] ETMP2[0] ETMP2[9] ETMP2[8] ITMP[6] ITMP[5] ITMP[4] REV[1] REV[0] THSD BIT 6 BIT 5 BIT 4 PEC[6] PEC[5] PEC[4] LTC6802-1 BIT 3 BIT 2 BIT 1 C2OV C2UV C1OV C6OV C6UV C5OV C10OV C10UV C9OV BIT 3 BIT 2 BIT 1 ETMP1[3] ETMP1[2] ETMP1[1] ETMP1[11] ETMP1[10] ...
Page 22
... LTC6802-1 APPLICATIONS INFORMATION Table 12. Memory Bit Descriptions NAME DESCRIPTION CDC Comparator Duty Cycle CELL10 10-Cell Mode LVLPL Level Polling Mode GPIO1 GPIO1 Pin Control GPIO2 GPIO2 Pin Control WDTEN Watchdog Timer Enable DCCx Discharge Cell x VUV Undervoltage Comparison Voltage* VOV Overvoltage Comparison Voltage* ...
Page 23
... APPLICATIONS INFORMATION SERIAL COMMAND EXAMPLES LTC6802-1 (Daisy Chained Confi guration) Examples below use a confi guration of three stacked devices: bottom (B), middle (M), and top (T) Write Confi guration Registers 1. Pull CSBI low 2. Send WRCFG command byte 3. Send CFGR0 byte for top device, then CFGR1 (T), CFGR2 (T), … CFGR5 (T) 4. Send CFGR0 byte for middle device, then CFGR1 (M), CFGR2 (M), … ...
Page 24
... Clamp diodes at each pin to V & V alternate power-path if there are other devices (which can supply power) connected to the LTC6802-1. Diode conduction at data ports will impair communication with higher-potential units. If the watchdog timer is enabled, all units above the disconnection will enter standby mode within 2 seconds of disconnect ...
Page 25
... The FMEA scenarios involving a break in the stack of battery cells are potentially the most damaging. In the case where the battery stack has a discontinuity between groupings of cells monitored by LTC6802-1 ICs, any load will force a large reverse potential on the daisy-chain connection. This situation might occur in a modular battery system during initial installation or a service procedure ...
Page 26
... Figure 13. Adding RC Filtering to the Cell Inputs (One Cell Connection Shown) READING EXTERNAL TEMPERATURE PROBES Using Dedicated Inputs The LTC6802-1 includes two channels of ADC input, V and V , that are intended to monitor thermistors TEMP2 (tempco about –4%/°C generally) or diodes (–2.2mV/°C typical) located within the cell array ...
Page 27
... PROVIDING HIGH-SPEED OPTO-ISOLATION OF THE SPI DATA-PORT Isolation techniques that are capable of supporting the 1Mbps data rate of the LTC6802-1 require more power on the isolated (battery) side than can be furnished by the V REG minimal, this means that a DC/DC function must be imple- ...
Page 28
... CELL1 100Ω Figure 18. Providing Measurement of Calibration Reference and Full-Stack Voltage Through CELL1 Port 3.57k 3.57k CSBI SDO SDI SCKI V REG 100nF 249Ω LTC6802-1 ISOLATED V 1μF − V Figure 19. Providing an Isolated High-Speed Data Interface 28 TP0610K 1M 2. REF_EN CELL1 STACK12 ...
Page 29
... PCB LAYOUT CONSIDERATIONS The V and V pins should be bypassed with a 1μF REG REF capacitor for best performance. The LTC6802-1 is capable of operation with as much as + – 60V between V and V . Care should be taken on the PCB layout to maintain physical separation of traces at different potentials. The pinout of the LTC6802-1 was chosen to facilitate this physical separation ...
Page 30
... ADC with a wide bandwidth (such as a SAR) preceded by a perfect 1350Hz brickwall lowpass fi lter. Thus if an analog fi lter is placed in front of a SAR converter to achieve the same noise rejection as the LTC6802-1 ADC – ...
Page 31
... THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE ** LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE † THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE LTC6802 7.40 – 8.20 (.291 – .323 ...
Page 32
... Multicell Battery Stack Monitor with Parallel Addressed Serial Interface Linear Technology Corporation 32 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● COMMENTS Functionality equivalent to LTC6802-1, Allows for Individually Addressable Battery Stack Topologies www.linear.com ● 68021p LT 0808 • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2008 ...