ltc6910-2 Linear Technology Corporation, ltc6910-2 Datasheet - Page 18

• Manufacturer Part Number: ltc6910-2
• Description: Digitally Controlled Programmable Gain Amplifiers In Sot-23
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC6910-1
LTC6910-2/LTC6910-3
Offset Nulling and Drift
Because internal op amp offset voltage V
independent as noted above, offset trimming can be
readily added at the AGND pin, which drives the noninverting
input of the internal op amp. Such a trim shifts the AGND
voltage slightly from the system’s analog ground refer-
ence, where AGND would otherwise connect directly. This
is convenient when a low resistance analog ground poten-
tial or analog ground reference exists, for the return of a
voltage divider as in Figure 5a. When adjusted for zero DC
output voltage when the LTC6910-X has zero DC input
voltage, this DC nulling will hold at other gain settings also.
Figure 5a shows the basic arrangement for dual-supply
applications. A voltage divider (R1 and R2) scales external
reference voltages +V
slightly exceeding the approximately 10mV op amp off-
set-voltage range. Resistor R1 is chosen to drop the
set to either end. Thus if V
100 . Note also that the two internal 10k resistors in
Figure 4 tend to bias AGND toward the mid-point of V
V
is much less than 5k . When considering the effect of the
internal 10k resistors, note that they form a Thévenin
equivalent of 5k in series with an open-circuit voltage at
the halfway potential (V
18
20k
10mV maximum trim voltage when the potentiometer is
–
+V
–V
. The external voltage divider will swamp this effect if R1
REF
REF
Figure 5a. Offset Nulling
49.9k
R2
(Dual Supplies)
R1
U
C1
ANALOG GROUND
REFERENCE
REF
1 F
+
+ V
2
and –V
AGND
U
LTC6910-X
–
REF
)/ 2. (Although tightly matched,
6910 F05a
is 5V, R1 should be about
REF
W
to a range equaling or
(Single Supply, Half Supply Reference)
OS(OA)
500
17.4k
17.4k
U
Figure 5b. Offset Nulling
is gain
+
and
1 F
these internal 10k resistors also have an absolute toler-
ance of up to 30% and a temperature coefficient of
typically –30ppm/ C.) Also, as described under Pin Func-
tions for AGND, a bypass capacitor C1 is always advisable
when AGND is not connected directly to a ground plane.
With this trim technique in place, the remaining DC offset
sources are drifts with temperature (typically 6 V/ C
referred to V
voltage divided by the PSRR factors, supply voltage shifts
coupling through the two 10k internal resistors of
Figure 4, and of course any shifts in the reference voltages
that supply +V
Figure 5b illustrates how to make an offset voltage adjust-
ment relative to the mid-supply potential in single supply
applications. Resistor values shown provide at least a
for the internal resistors at pin 2 and a supply potential of
5V. For single supply systems where all circuitry is DC
referenced to some other fixed bias potential, an offset
adjustment scheme is shown in Figure 5c. A low value for
R1 overrides the internal resistors at pin 2 and applies the
system DC bias to the LTC6910. Actual values for the
adjustment components depend on the magnitude of the
DC bias voltage. Offset adjustment component values
shown are an example with a single 5V V
1.25V system DC reference voltage.
10mV adjustment range assuming the minimum values
2
AGND
LTC6910-X
V
CC
8
4
5V
6910 F05b
OS(OA)
REF
and –V
), shifts in the LTC6910-X’s supply
(Single Supply, External Reference)
500
976
4.64k
REF
V
CC
Figure 5c. Offset Nulling
in Figure 5a.
5V
SYSTEM DC REFERENCE
100
VOLTAGE
R1
1.25V
1 F
CC
supply and a
2
AGND
LTC6910-X
V
CC
8
4
6910123fa
5V
6910 F05c