ltc4259a Linear Technology Corporation, ltc4259a Datasheet - Page 24

• Manufacturer Part Number: ltc4259a
• Description: Quad Ieee 802.3af Power Over Ethernet Controller With Ac Disconnect
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC4259A
lines, SDA and SCL, must be high when the bus is not in
use. External pull-up resistors or current sources, such as
the LTC1694 SMBus accelerator, are required on these
lines. If the SDA and SCL pull-ups are absent, not con-
nected to the same positive supply as the LTC4259A’s V
pin, or are not activated when the power is applied to the
LTC4259A, it is possible for the LTC4259A to see a START
condition on the I
updated between I
LTC4259A sees a START condition when it powers up
because the SCL and SDA lines were left floating, it will not
assert an interrupt (pull INT low) until it sees a STOP
condition on the bus. In a typical application the I
will immediately have traffic and the LTC4259A will see a
STOP so soon after power up that this momentary condi-
tion will go unnoticed.
Isolating the Serial Digital Interface
IEEE 802.3af requires that network segments be electri-
cally isolated from the chassis ground of each network
interface device. However, the network segments are not
required to be isolated from each other provided that the
segments are connected to devices residing within a
single building on a single power distribution system.
For simple devices such as small powered Ethernet
switches, the requirement can be met by using an iso-
lated power supply to power the entire device. This
implementation can only be used if the device has no
electrically conducting ports other than twisted-pair Eth-
ernet. In this case, the SDAIN and SDAOUT pins of the
LTC4259A can be connected together to act as a standard
I
If the device is part of a larger system, contains serial
ports, or must be referenced to protective ground for
some other reason, the Power over Ethernet subsystem
including the LTC4259As must be electrically isolated
from the rest of the system. The LTC4259A includes
separate pins (SDAIN and SDAOUT) for the input and
output functions of the bidirectional data line. This eases
the use of optocouplers to isolate the data path between
the LTC4259As and the system controller. Figure 20
shows one possible implementation of an isolated inter-
face. The SDAOUT pin of the LTC4259A is designed to
24
2
C/SMBus SDA pin.
2
C bus. The interrupt pin (INT) is only
U
2
C transactions. Therefore if the
U
W
U
2
C bus
DD
drive the inputs of an optocoupler directly, but a standard
I
signals into the optocouplers from the system controller
side. Schmitt triggers must be used to prevent extra
edges on transitions of SDA and SCL.
Bus Addresses and Protocols
The LTC4259A is a read-write slave device. The master
can communicate with the LTC4259A using the Write
Byte, Read Byte and Receive Byte protocols. The
LTC4259A’s primary serial bus address is
(010A
LTC4259As also respond to the address (0110000)b,
allowing the host to write the same command into all of
the LTC4259As on a bus in a single transaction. If the
LTC4259A is asserting (pulling low) the INT pin, it will
also acknowledge the Alert Response Address (0001100)b
using the receive byte protocol.
The START and STOP Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master (typically the host controller) signals the
beginning of communication with a slave device (like the
LTC4259A) by transmitting a START condition. A START
condition is generated by transitioning SDA from high to
low while SCL is high. A REPEATED START condition is
functionally the same as a START condition, but used to
extend the protocol for a change in data transmission
direction. A STOP condition is not used to set up a
REPEATED START condition, for this would clear any data
already latched in. When the master has finished commu-
nicating with the slave, it issues a STOP condition. A STOP
condition is generated by transitioning SDA from low to
high while SCL is high. The bus is then free for communi-
cation with another SMBus or I
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The corresponding SCL
clock pulse is always generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
2
C device typically cannot. U1 is used to buffer I
3
A
2
A
1
A
0
)b, as designated by pins AD3-AD0. All
2
C device.
4259afb
2
C