ltc4264cde-trpbf Linear Technology Corporation, ltc4264cde-trpbf Datasheet - Page 3

• Manufacturer Part Number: ltc4264cde-trpbf
• Description: High Power Pd Interface Controller With 750ma Current Limit
• Manufacturer: Linear Technology Corporation

ELECTRICAL CHARACTERISTICS
SYMBOL
V
V
I
V
V
I
R
I
I
I
I
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and
lifetime.
Note 2: All voltages are with respect to GND pin unless otherwise noted.
Note 3: Active high PWRGD pin internal clamp circuit self-regulates to 14V
with respect to V
Note 4: The LTC4264 operates with a negative supply voltage in the range of
–1.5V to –57V. To avoid confusion, voltages in this data sheet are referred to
in terms of absolute magnitude.
Note 5: In IEEE 802.3af systems, the maximum voltage at the PD jack is
defi ned to be –57V. See Applications Information.
Note 6: The LTC4264 is designed to work with two polarity protection
diodes in series with the input. Parameter ranges specifi ed in the Electrical
Characteristics are with respect to LTC4264 pins and are designed to meet
IEEE 802.3af specifi cations when the drop from the two diodes is included.
See Applications Information.
Note 7: Signature resistance is measured via the two-point ΔV/ΔI method
as defi ned by IEEE 802.3af. The LTC4264 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifi cations. The minimum probe voltages measured at the LTC4264 pins
are – 1.5V and – 2.5V. The maximum probe voltages are –9.1V and –10.1V.
Note 8: The LTC4264 includes hysteresis in the UVLO voltages to preclude
any start-up oscillation. Per IEEE 802.3af requirements, the LTC4264 will
power up from a voltage source with 20Ω series resistance on the fi rst trial.
Note 9: I
Pin 3. Total supply current in classifi cation mode will be I
(see Note 10).
Note 10: I
accuracy is with respect to the ideal current defi ned as I
temperature range, otherwise specifi cations are at T
PWRGD_LEAK
PWRGD_LEAK
OUT_LEAK
LIMIT_HIGH
LIMIT_LOW
LIMIT_DISA
IL_ILIM
PWRGD_OUT
PWRGD_OUT
PWRGD_VCLAMP
ON
IN_CLASS
CLASS
is the measured current fl owing through R
OUT
does not include classifi cation current programmed at
PARAMETER
I
Active Low Power Good
Output Low Voltage
Active Low Power Good Leakage
Active High Power Good
Output Low Voltage
Active High Power Good
Voltage-Limiting Clamp
Active High Power Good Leakage
On Resistance
V
Input Current Limit During Normal
Operation
Inrush Current Limit
Safeguard Current Limit when
I
LIM_EN
LIMIT_HIGH
.
OUT
Leakage
Low Level Input Voltage
Disabled
CLASS
IN_CLASS
CLASS
= 1.237/R
CONDITIONS
With Respect to V
I
Referenced to V
V
I
PWRGD Referenced to V
I
With Respect to V
V
V
I = 700mA, V
Measured from V
V
V
(Notes 15, 16)
V
V
(Notes 15, 16, 17)
A
PWRGD
PWRGD
PWRGD
IN
PWRGD
OUT
IN
IN
IN
IN
. ΔI
= 25°C. (Note 4)
+ I
= 0V, V
= –57V, GND = SHDN = V
= –54V, V
= –54V, V
= –54V, V
CLASS
= V
CLASS
= 1mA, V
= 0.5mA, V
= 2mA, V
The
= 11V, with Respect to V
CLASS
IN
PWRGD
= –54V
●
IN
OUT
OUT
OUT
.
denotes the specifi cations which apply over the full operating
= –54V
IN
IN
OUT
IN
= –53V, I
= –53V (Notes 15, 16)
= –52.5V, I
IN
OUT
= 57V
IN
= –54V, ⎯ P ⎯ W ⎯ R ⎯ G ⎯ D
to V
t
accuracy specifi cation does not include variations in R
total classifi cation current for a PD also includes the IC quiescent current
(I
Note 11: This parameter is assured by design and wafer level testing.
Note 12: To disable the 25k signature, tie SHDN to GND (±0.1V) or hold SHDN
pin high with respect to V
Note13: I
be left fl oating. To disable high level current limit, tie I
Applications Information.
Note 14: Active high power good is referenced to V
GND-V
Note 15: The LTC4264 includes a dual current limit. At turn-on, before C1 is
charged, the LTC4264 current level is set to I
and with I
pin tied low, the LTC4264 switches to I
I
off threshold or a thermal overload occurs.
Note 16: The LTC4264 features thermal overload protection. In the event of
an overtemperature condition, the LTC4264 will turn off the power MOSFET,
disable the classifi cation load current and present an invalid power good
signal. Once the LTC4264 cools below the overtemperature limit, the
LTC4264 current limit switches to I
Thermal overload protection is intended to protect the device during
momentary fault conditions and continuous operation in thermal overload
should be avoided as it may impair device reliability.
Note 17: I
normal input current limit (I
Currents at or near I
require a reduced maximum ambient operating temperature in order to avoid
tripping the thermal overload protection. See Applications Information.
(Note 13)
CLASSRDY
LIMIT_HIGH
= 0V,
= –52V, V
IN_CLASS
(Note 3)
OUT
OUT
LIM_EN
OUT
(Note 11)
LIM_EN
(Note 14)
OUT
LIM_EN
LIM_EN
LIMIT_DISA
). See Applications Information.
is the time for I
OUT
≥ 4V. Measured at –52V due to test hardware limitations.
or I
OUT
= 0V
Floating
LIMIT_DISA
= –4V,
Tied to V
pin is pulled high internally and for normal operation should
,
fl oating, the LTC4264 switches to I
LIMIT_DISA
is a safeguard current limit that is activated when the
IN
IN
CLASS
until the input voltage drops below the UVLO turn-
. See Applications Information.
LIMIT_HIGH
will cause signifi cant package heating and may
●
●
●
●
●
●
●
●
●
●
to settle to within ±3.5% of ideal. The current
LIMIT_LOW
MIN
12.0
1.20
700
250
) is defeated using the I
LIMIT_DISA
LIMIT_LOW
and normal operation resumes.
. The LTC4264 stays in
14.0
1.45
TYP
750
300
0.5
OUT
LIMIT_HIGH
LIM_EN
LTC4264
. After C1 is charged
CLASS
and is valid for
MAX
to V
0.35
16.5
1.65
800
350
resistance. The
0.5
0.6
0.8
LIM_EN
1
1
1
1
. With I
IN
. See
pin.
LIM_EN
UNITS
3
4264f
mA
mA
µA
µA
µA
Ω
Ω
V
V
V
V
A