ltc3900 Linear Technology Corporation, ltc3900 Datasheet - Page 7

• Manufacturer Part Number: ltc3900
• Description: Synchronous Rectifier Driver For Forward Converters
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
When the primary controller is powering down, the pri-
mary controller shuts down first and the LTC3900 contin-
ues to operate for a while by drawing power from the V
bypass cap, C
is no SYNC pulse to the LTC3900. The LTC3900 keeps one
of the drivers turned on depending on the polarity of the
last SYNC pulse. If the last SYNC pulse is positive, CG will
remain high and the catch MOSFET, Q4 will stay on. The
inductor current will start falling down to zero and con-
tinue going in the negative direction due to the voltage that
is still present across the output capacitor (the current
now flows from C
the inductor current is negative, the inductor current will
produce high voltage across Q4, resulting in a MOSFET
avalanche. Depending on the amount of energy stored in
the inductor, this avalanche energy may damage Q4.
The timer circuit and current sense comparator in LTC3900
are used to prevent reverse current buildup in the output
inductor.
Timer
Figure 3 shows the LTC3900 timer internal and external
circuits. The timer operates by using an external R-C
charging network to program the time-out period. On
every negative transition at the SYNC input, the chip
generates a 200ns pulse to reset the timer cap. If the SYNC
signal is missing or incorrect, allowing the timer cap
voltage to go high, it shuts off both drivers once the
voltage reaches the time-out threshold. Figure 4 shows
the timer waveforms.
Burst Mode is a registered trademark of Linear Technology Corporation.
(S
(OUT)
SYNC
GATE
OUT
SG
CG
FG
)
Figure 2. Synchronization Waveforms
VCC
. The SG signal stops switching and there
OUT
U
back to L
U
O
). If Q4 is turned off while
W
3900 F02
U
CC
A typical forward converter cycle always turns on Q3 and
Q4 alternately and the SYNC input should alternate be-
tween positive and negative pulses. The LTC3900 timer
also includes sequential logic to monitor the SYNC input
sequence. If after one negative pulse, the SYNC compara-
tor receives another negative pulse, the LTC3900 will not
reset the timer cap. If no positive SYNC pulse appears,
both drivers are shut off once the timer times out. Once
positive pulses reappear the timer resets and the drivers
start switching again. This is to protect the external
components in situations where only negative SYNC pulse
is present and FG output remains high. Figure 5 shows the
timer waveforms with incorrect SYNC pulses.
The LTC3900 has two separate SYNC comparators (S
and S
negative pulses. The threshold voltages of both compara-
tors are designed to be of the same magnitude (1.4V
typical) but opposite in polarity. In some situations, for
example during power up or power down, the SYNC pulse
magnitude may be low, slightly higher or lower than the
TIMER RESET
(INTERNAL)
–
in the Block Diagram) to detect the positive and
TIMER
SYNC
FG
CG
SG
TIMEOUT
TIMER
RESET
Figure 4. Timer Waveforms
Figure 3. Timer Circuit
TMR
R2
R1
Z
TMR
3900 F03
7
4
LTC3900
V
CC
R
TMR
C
THRESHOLD
TMR
TIMEOUT
LAST
PULSE
3900 F04
7
3900f
+