ltc2195 Linear Technology Corporation, ltc2195 Datasheet - Page 14

• Manufacturer Part Number: ltc2195
• Description: Ltc2195/ltc2194/ltc2193 - 16-bit, 125/105/80msps Low Power Dual Adcs
• Manufacturer: Linear Technology Corporation

PIN FUNCTIONS
LTC2195
LTC2194/LTC2193
V
to V
of the analog inputs of channel 1. Bypass to ground with
a 0.1µF ceramic capacitor.
GND (Pins 2, 5, 13, 22, 45, 47, 49, Exposed Pad Pin 65):
ADC Power Ground. The exposed pad must be soldered
to the PCB ground.
A
Input.
A
Input.
REFH (Pins 6, 8): ADC High Reference. See the Reference
section in the Applications Information for recommended
bypassing cIrcuits for REFH and REFL.
REFL (Pins 7, 9): ADC Low Reference. See the Reference
section in the Applications Information for recommended
bypassing cIrcuits for REFH and REFL.
PAR/SER (Pin 10): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to V
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the V
by a logic signal.
A
Input.
A
Input.
V
Equal to V
mode of the analog inputs of channel 2. Bypass to ground
with a 0.1µF ceramic capacitor.
V
to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
14
CM1
IN1
IN1
IN2
IN2
CM2
DD
DD
+ (Pin 3): Channel 1 Positive Differential Analog
– (Pin 4): Channel 1 Negative Differential Analog
+ (Pin 11): Channel 2 Positive Differential Analog
– (Pin 12): Channel 2 Negative Differential Analog
(Pins 15, 16, 51, 52): Analog Power Supply, 1.7V
(Pin 1): Common Mode Bias Output, Nominally Equal
(Pin 14): Common Mode Bias Output, Nominally
/2. V
DD
CM1
/2. V
should be used to bias the common mode
CM2
should be used to bias the common
DD
of the part and not be driven
DD
to enable the
ENC
rising edge.
ENC
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 19): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = V
2- or 4-lane output mode (see Table 3). CS can be driven
with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = V
selects 1-, 2- or 4-lane output mode (see Table 3). SCK
can be driven with 1.8V to 3.3V logic.
SDI (Pin 21): In Serial Programming Mode, (PAR/SER =
0V), SDI is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming pode (PAR/SER
= V
be driven with 1.8V to 3.3V logic.
OGND (Pin 33): Output Driver Ground. This pin must be
shorted to the ground plane by a very low inductance path.
Use multiple vias close to the pin.
OV
with a 0.1µF ceramic capacitor.
SDO (Pin 46): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control regis-
ters and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V to 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = V
3.5mA or 1.75mA LVDS output currents. When used as an
input, SDO can be driven with 1.8V to 3.3V logic through
a 1k series resistor.
DD
DD
+
–
), SDI can be used to power down the part. SDI can
(Pin 17): Encode Input. Conversion starts on the
(Pin 18): Encode Complement Input. Conversion
(Pin 34): Output Driver Supply. Bypass to ground
DD
), CS along with SCK selects 1-,
DD
), SCK along with CS
DD
), SDO selects
219543p