ltc2484 Linear Technology Corporation, ltc2484 Datasheet - Page 23

• Manufacturer Part Number: ltc2484
• Description: 24-bit Delta Sigma Adc With Easy Drive Input Current Cancellation
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
(INTERNAL)
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time t
after the falling edge of CS (if EOC = 0) or t
goes LOW (if CS is LOW during the falling edge of EOC).
The value of t
oscillator. If F
frequency f
is pulled HIGH before time t
the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 32nd rising edge. The input data is shifted in via
the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
SDO
SCK
SDI
CS
CONVERSION
Hi-Z
DON’T CARE
EOSC
EOCtest
O
SLEEP
, then t
TEST EOC
is driven by an external oscillator of
U
is 12µs if the device is using its internal
SLEEP
Hi-Z
EOCtest
<t
EOCtest
U
BIT 31
EOC
EOCtest
EN
is 3.6/f
BIT 30
EOCtest
, the device returns to
W
Figure 8. Internal Serial Clock, Single Cycle Operation
EOSC
DON’T CARE
BIT 29
in seconds. If CS
EOCtest
, the first rising
SIG
U
BIT 28
MSB
after EOC
EOCtest
0.1V TO V
REFERENCE
VOLTAGE
ANALOG
BIT 27
INPUT
1µF
2.7V TO 5.5V
IM
CC
DATA OUTPUT
2
3
4
5
BIT 26
V
V
IN
IN
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 32nd rising edge of
SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1), SCK stays HIGH and a new conversion starts.
CS remains LOW during the data output state. However,
the data output state may be aborted by pulling CS HIGH
anytime between the first and 32nd rising edge of SCK (see
Figure 9). On the rising edge of CS, the device aborts the
data output state and immediately initiates a new conver-
sion. If the device has not finished loading the last input bit
(SPD) of SDI by the time CS is pulled HIGH, the SDI
information is discarded and the previous configuration is
still kept. This is useful for systems not requiring all 32 bits
of output data, aborting an invalid conversion cycle, or
synchronizing the start of a conversion. If CS is pulled
HIGH while the converter is driving SCK LOW, the internal
pull-up is not available to restore SCK to a logic HIGH state.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS HIGH when SCK is LOW.
FOA
CC
REF
+
–
LTC2484
BIT 25
GND
SDO
SCK
SDI
CS
F
FOB
O
7
8
10
1
9
6
BIT 24
SPD
INT/EXT CLOCK
4-WIRE
SPI INTERFACE
V
CC
DON’T CARE
BIT 5
10k
LSB
BIT 0
LTC2484
CONVERSION
Hi-Z
23
TEST EOC
2484fa
2484 F08
Hi-Z