ltc2633-lz8 Linear Technology Corporation, ltc2633-lz8 Datasheet - Page 18

• Manufacturer Part Number: ltc2633-lz8
• Description: Dual 12-/10-/8-bit I2c Vout Dacs With 10ppm/?c Reference
• Manufacturer: Linear Technology Corporation

LTC2633
operation
The format of the three data bytes is shown in Figure
3. The first byte of the input word consists of the 4-bit
command, followed by the 4-bit DAC address. The next
two bytes contain the 16-bit data word, which consists
of the 12-, 10- or 8-bit input code, MSB to LSB, followed
by 4, 6 or 8 don’t-care bits (LTC2633-12, LTC2633-10
and LTC2633-8 respectively). A typical LTC2633 write
transaction is shown in Figure 4.
The command bit assignments (C3-C0) and address (A3-
A0) assignments are shown in Tables 3 and 4. The first
four commands in the table consist of write and update
operations. A write operation loads a 16-bit data word
from the 32-bit shift register into the input register. In an
update operation, the data word is copied from the input
register to the DAC register. Once copied into the DAC
register, the data word becomes the active 12-, 10-, or
8-bit input code, and is converted to an analog voltage at
the DAC output. Write to and update combines the first
two commands. The update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
18
WRITE WORD PROTOCOL LTC2633
INPUT WORD (LTC2633-12)
INPUT WORD (LTC2633-10)
INPUT WORD (LTC2633-8)
C3
C3
C3
S
C2
C2
C2
SLAVE ADDRESS
C1
C1
C1
1ST DATA BYTE
1ST DATA BYTE
1ST DATA BYTE
C0
C0
C0
A3
A3
A3
A2
A2
A2
W
A1
A1
A1
A
A0
A0
A0
1ST DATA BYTE
Figure 3. Command and Data Input Format
D11
D9
D7
D10
D8
D6
D9
D7
D5
A
2ND DATA BYTE
2ND DATA BYTE
2ND DATA BYTE
D8
D6
D4
2ND DATA BYTE
INPUT WORD
D7
D5
D3
Table 3. Command Codes
*Command codes not shown are reserved and should not be used.
Table 4. Address Codes
* Address codes not shown are reserved and should not be used.
C3
A3
0
0
0
0
0
0
0
0
1
0
0
1
ADDRESS (n)*
COMMAND*
D6
D4
D2
C2
A2
0
0
0
0
1
1
1
1
1
0
0
1
D5
D3
D1
A
C1
A1
0
0
1
1
0
0
1
1
1
0
0
1
D4
D2
D0
3RD DATA BYTE
C0
A0
0
1
0
1
0
1
0
1
1
0
1
1
D3
D1
X
Write to Input Register n
Update (Power-Up) DAC Register n
Write to Input Register n, Update (Power-Up) All
Write to and Update (Power-Up) DAC Register n
Power-Down n
Power-Down Chip (All DAC’s and Reference)
Select Internal Reference (Power-Up Reference)
Select External Reference (Power-Down Internal
Reference)
No Operation
DAC A
DAC B
All DACs
D2
D0
X
D1
A
X
X
3RD DATA BYTE
3RD DATA BYTE
3RD DATA BYTE
D0
P
X
X
X
X
X
X
X
X
X
X
X
2633 F03
X
X
X
2633fb