ds4302 Maxim Integrated Products, Inc., ds4302 Datasheet - Page 7

• Manufacturer Part Number: ds4302
• Description: Ds4302 2-wire, 5-bit Dac With Three Digital Outputs
• Manufacturer: Maxim Integrated Products, Inc.

Figure 3. 2-Wire Timing Diagram
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (see Figure 3) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses including when it is reading bits from
the slave.
Acknowledgement (ACK): An Acknowledgement
(ACK) is always the 9th bit transmitted during a byte
transfer. The device receiving data (the master during a
read or the slave during a write operation) performs an
ACK by transmitting a zero during the 9th bit. For tim-
ing, see Figure 3. An ACK is the acknowledgement that
the device is properly receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK from the
master to the slave. The 8 bits of information that are
transferred (most significant bit first) from the slave to
the master are read by the master using the bit read
definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must ACK the last byte read to termi-
nated communication so the slave returns control of
SDA to the master.
SDA
SCL
NOTE: TIMING IS REFERENCE TO V
STOP
2-Wire, 5-Bit DAC with Three Digital Outputs
t
BUF
START
IL(MAX)
t
HD:STA
t
LOW
AND V
IH(MIN)
.
_____________________________________________________________________
t
R
t
HD:DAT
t
F
t
HIGH
t
SU:DAT
Slave Address and the
2-wire bus responds to a slave addressing byte sent
immediately following a START condition. The slave
address byte contains the slave address and the R/W
bit. The slave address (see Figure 4) is the most signifi-
cant 7 bits and the R/W bit is the least significant bit.
The DS4302’s slave address is 0101100X (binary),
where X is the R/W bit. If the R/W bit is zero
(01011000), the master will write data to the slave. If the
R/W is a one (01011001), the master will read data from
the slave.
Memory Address: During a 2-wire write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is the second byte transmitted
during a write or read operation following the slave
address byte (R/W=0). For a write operation, the mem-
ory address is 10101010 (AAh) and for a read opera-
tion, the memory address is 00000000 (00h).
Figure 4. Slave Address and the R/ W Bit
REPEATED
START
MOST
SIGNIFICANT
BIT
t
SU:STA
t
HD:STA
0
1
7-BIT SLAVE ADDRESS
0
1
1
R/W Bit: Each slave on the
0
0
R/W
t
SP
READ OR WRITE
DETERMINES
t
SU:STO
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