mcf52110 Freescale Semiconductor, Inc, mcf52110 Datasheet - Page 5

• Manufacturer Part Number: mcf52110
• Description: Mcf52110 Coldfire Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

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The MCF52110 family includes the following features:
Freescale Semiconductor
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Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— 40 MHz and 33 MHz off-platform bus frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16×16 → 32 or 32×32 → 32 operations
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can be configured into
On-chip memories
— 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply
— Up to 128 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used (except backup watchdog timer)
— Software controlled disable of external clock output for low-power consumption
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
Two I
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I
— Master and slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable bit rates up to half the CPU clock frequency
— Up to 16 pre-programmed transfers
for improved bit processing (ISA_A+)
a 1- or 2-level trigger
support
Feature Overview
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C modules
MCF52110 ColdFire Microcontroller, Rev. 0
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C bus
MCF52110 Family Configurations
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