nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 38

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 6 8-Bit Arithmetic
Timing
Addressing Mode
NEG
Negate the Accumulator (2’s complement)
A
Timing
Addressing Mode
CCF
Complement the carry flag
CY
Timing
Addressing Mode
SCF
Set the carry flag
CY
Timing
Addressing Mode
7
0
7
1
0
7
0
7
0
6
0
6
1
1
6
0
6
0
0
5
1
5
1
0
5
1
5
1
CY
1
b
4
0
A
4
0
0
4
1
4
1
3
1
3
1
0
3
1
3
0
2
1
2
1
1
2
1
2
1
P V Set only if Accumulator was
P V N A
P V N A
1
1
1
0
0
1
1
1
1
H Set according to borrow from
N Set
C Set only if Accumulator was not
H Previous carry
N Reset
C Complement of previous carry
H Reset
N Reset
C Set
S Set if result is negative
Z Set if result is zero
S N A
Z N A
S N A
Z N A
0
1
0
1
0
0
1
0
1
M cycles 1
T states 4
Implied
bit 4
X’80 prior to operation
X’00 prior to operation
M cycles 2
T states 8 (4 4)
Implied
M cycles 1
T states 4
Implied
M cycles 1
T states 4
Implied
(Continued)
38
DAA
Adjust the Accumulator for BCD addition and subtraction
operations To be executed after BCD data has been oper-
ated upon the standard binary ADD ADC INC SUB SBC
DEC or NEG instructions (see ‘‘Register Addressing Arith-
metic’’ table)
Timing
Addressing Mode
IMMEDIATELY ADDRESSED ARITHMETIC
ADD
Add the immediate data n to the Accumulator
A
Timing
Addressing Mode
ADC
Add with carry the immediate data n and the Accumulator
A
7
0
7
1
6
0
6
1
A
A
5
1
5
0
A n
A n
a
a
4
0
4
0
n
n
n
a
3
0
3
0
CY
2
1
2
1
P V Set according to parity of result
P V Set if result exceeds 8-bit 2’s
P V Set if result exceeds 8-bit 2’s
1
1
1
1
N N A
N Reset
N Reset
S Set according to bit 7 of result
H Set according to instructions
C Set according to instructions
S Set if result is negative
H Set if carry from bit 3
C Set if carry from bit 7
S Set if result is negative
H Set if carry from bit 3
C Set according to carry from bit
Z Set if result is zero
Z Set if result is zero
Z Set if result is zero
0
1
0
0
M cycles 1
T states 4
Implied
complement range
M cycles 2
T states 7 (4 3)
Source Immediate
Destination Implied
complement range
7