ltc2226iuh-trpbf Linear Technology Corporation, ltc2226iuh-trpbf Datasheet - Page 21

• Manufacturer Part Number: ltc2226iuh-trpbf
• Description: Ltc2227 - 12-bit, 40msps Low Power 3v Adcs
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2228/LTC2227/
LTC2226 is 65Msps (LTC2228), 40Msps (LTC2227), and
25Msps (LTC2226). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each half
cycle must have at least 7.3ns (LTC2228), 11.8ns
(LTC2227), and 18.9ns (LTC2226) for the ADC internal
circuitry to have enough settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3V
The lower limit of the LTC2228/LTC2227/LTC2226 sample
rate is determined by droop of the sample-and-hold cir-
cuits. The pipelined architecture of this ADC relies on
storing analog signals on small valued capacitors. Junc-
tion leakage will discharge the capacitors. The specified
minimum operating frequency for the LTC2228/LTC2227/
LTC2226 is 1Msps.
LATCH
FROM
DATA
OE
PREDRIVER
LOGIC
V
DD
Figure 14. Digital Output Buffer
DD
U
or 2/3V
U
V
DD
DD
using external resistors.
W
LTC2228/27/26
OV
DD
43Ω
222876 F14
OV
U
OGND
DD
TYPICAL
DATA
OUTPUT
0.1µF
0.5V
TO 3.6V
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
Table 1. Output Codes vs Input Voltage
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2228/LTC2227/LTC2226 should
drive a minimal capacitive load to avoid possible interac-
tion between the digital outputs and sensitive input cir-
cuitry. The output should be buffered with a device such as
an ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
from the digital outputs.
Table 2. MODE Pin Function
MODE Pin
0
1/3V
2/3V
V
>+1.000000V
<–1.000000V
LTC2228/LTC2227/LTC2226
DD
A
(2V Range)
+0.999512V
+0.999024V
+0.000488V
–0.000488V
–0.000976V
–0.999512V
–1.000000V
0.000000V
IN
DD
DD
+
– A
IN
–
DD
voltages will also help reduce interference
2’s Complement
2’s Complement
Output Format
OF
1
0
0
0
0
0
0
0
0
1
Offset Binary
Offset Binary
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
(Offset Binary)
D11 – D0
Cycle Stablizer
DD
Clock Duty
(2’s Complement)
and OGND, iso-
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
Off
Off
On
On
D11 – D0
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