ltc2220cup-trpbf Linear Technology Corporation, ltc2220cup-trpbf Datasheet - Page 23

• Manufacturer Part Number: ltc2220cup-trpbf
• Description: Ltc2221 - 12-bit, 135msps Adcs
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require one
hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3V
resistors.
The lower limit of the LTC2220/LTC2221 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2220/LTC2221 is 1Msps.
DIGITAL OUTPUTS
Table 1. Output Codes vs Input Voltage
>+1.000000V
<–1.000000V
A
(2V Range)
+0.999512V
+0.999024V
+0.000488V
–0.000488V
–0.000976V
–0.999512V
–1.000000V
0.000000V
IN
Figure 12b. ENC Drive Using a CMOS to PECL Translator
+
– A
IN
–
Figure 12a. Single-Ended ENC Drive,
V
THRESHOLD
Not Recommended for Low Jitter
MC100LVELT22
OF
1
0
0
0
0
0
0
0
0
1
U
= 1.6V
D0
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
(Offset Binary)
3.3V
0.1µF
D11 – D0
U
Q0
Q0
DD
1.6V
130Ω
83Ω
or 2/3V
ENC
ENC
3.3V
+
–
W
LTC2220/
LTC2221
ENC
ENC
130Ω
83Ω
22201 F12Ía
DD
+
–
(2’s Complement)
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
LTC2220/
using external
LTC2221
D11 – D0
22201 F12b
U
Digital Output Modes
The LTC2220/LTC2221 can operate in several digital out-
put modes: LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternate clock cycles (interleaved mode) or simultaneously
(simultaneous mode). For details on the clock timing, refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should be
connected to GND, 1/3V
resistor divider can be used to set the 1/3V
logic values. Table 2 shows the logic states for the LVDS
pin.
Table 2. LVDS Pin Function
LVDS
GND
1/3V
2/3V
V
Digital Output Buffers (CMOS Modes)
Figure 13a shows an equivalent circuit for a single output
buffer in the CMOS output mode. Each buffer is powered
by OV
power and ground. The additional N-channel transistor in
the output driver allows operation down to voltages as low
as 0.5V. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
DD
DD
DD
LATCH
FROM
DATA
DD
OE
Figure 13a. Digital Output Buffer in CMOS Mode
and OGND, which are isolated from the ADC
PREDRIVER
LOGIC
V
Digital Output Mode
Full-Rate CMOS
Demultiplexed CMOS, Simultaneous Update
Demultiplexed CMOS, Interleaved Update
LVDS
DD
LTC2220/LTC2221
DD
V
, 2/3V
DD
DD
LTC2220/LTC2221
OV
or V
DD
43Ω
22201 F13a
DD
DD
. An external
OV
OGND
DD
or 2/3V
TYPICAL
DATA
OUTPUT
0.5V
TO 3.6V
0.1µF
23
22201fa
DD