ltc1855 Linear Technology Corporation, ltc1855 Datasheet

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... Power dissipation is 40mW at 100ksps and lower in two power shutdown modes (27.5mW in Nap mode and 40mW in Sleep mode.) DC specifications include ±3LSB INL for the LTC1856, ±1.5LSB INL for the LTC1855 and ±1LSB for the LTC1854. The internal clock is trimmed for 5ms maximum conver- sion time and the sampling rate is guaranteed at 100ksps ...

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... Digital Input Voltage (Note 4) ...... (DGND – 0.3V) to 10V Digital Output Voltage .... (DGND – 0.3V) to (DV Power Dissipation .............................................. 500mW Operating Temperature Range LTC1854C/LTC1855C/LTC1856C ............ 0∞C to 70∞C LTC1854I/LTC1855I/LTC1856I .......... – 40∞C to 85∞C Storage Temperature Range ................. – 65∞C to 150∞C Lead Temperature (Soldering, 10 sec) ................. 300∞ ...

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... Input Signal –120 1 –70 60 Full-Scale Step 4 (Note 9) (Note 12) 150 MIN TYP MAX ±10 ±2.048 – ADC ±1 ● LTC1855 LTC1856 MIN TYP MAX MIN TYP MAX 83 87 –95 –101 –99 –103 –120 –120 1 1 –70 – ...

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... LTC1854/LTC1855/LTC1856 TER AL REFERE CE CHARACTERISTICS full operating temperature range, otherwise specifications are at T PARAMETER V Output Voltage REF V Output Temperature Coefficient REF V Output Impedance REF V Output Voltage REFCOMP U U DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, otherwise specifications are at T ...

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... Note 8: Bipolar zero error is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11 1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111 = DD 1111 1111 for the LTC1854 ...

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... CODE 185456 G07 6 LTC1856 Typical DNL Curve 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –32768 –16384 0 16384 CODE LTC1855 Typical DNL Curve 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 8191 –8192 0 –4096 4096 CODE LTC1854 Typical DNL Curve 1.0 0.8 0.6 0.4 0.2 0 –0.2 – ...

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... G16 LTC1854/LTC1855/LTC1856 LTC1856 Total Harmonic Distortion vs Input Frequency –70 –80 –90 –100 –110 100 1 10 INPUT FREQUENCY (kHz) LTC1855 Total Harmonic Distortion vs Input Frequency –60 –70 –80 –90 –100 –110 1 10 100 INPUT FREQUENCY (kHz) LTC1854 Total Harmonic Distortion vs Input Frequency – ...

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... TEMPERATURE (°C) 185456 G22 Supply Current vs Supply Voltage 9 100kHz SAMPLE 8.5 8.0 7.5 7.0 4.5 4.75 SUPPLY VOLTAGE (V) 8 LTC1855 Channel-to-Channel Gain Error Matching vs Temperature 0.5 0.25 0 –0.25 –0.5 100 –50 – TEMPERATURE (°C) Change in REFCOMP Voltage vs Load Current 0.04 0.02 0 –0.02 –0.04 –50 – ...

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... ADC (Pin 12): Positive Analog Input to the Analog-to- Digital Converter. – ADC (Pin 13): Negative Analog Input to the Analog-to- Digital Converter. LTC1854/LTC1855/LTC1856 AGND1 (Pin 14): Analog Ground. V (Pin 15): 2.5V Reference Output. Bypass to analog REF ground with a 1mF tantalum capacitor. REFCOMP (Pin 16): Reference Buffer Output. Bypass to analog ground with a 10mF tantalum and a 0 ...

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... LTC1854/LTC1855/LTC1856 CTIO S DGND (Pin 24): Digital Ground. SDI (Pin 25): Serial Data Input. SCK (Pin 26): Serial Data Clock CTIO AL BLOCK DIAGRA 2 CH0 3 CH1 • INPUT MUX • • 9 CH7 1 COM – MUXOUT 14 11 AGND1 10 RD (Pin 27): Read Input. This active low signal enables the digital output pin SDO and enables the serial interface, SDI and SCK are ignored when RD is high ...

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... Timing SCK (SDO Valid After 0.4V Hi-Z SDO LTC1854/LTC1855/LTC1856 25pF 18545 TC01 CONVST 50% BUSY 18545 TD01 t t (Time from Previous Data Remains Valid After SCK ) 7 SCK SDO 18545 TD03 RD 2.4V SCK 0.4V 18545 TD05 Load Circuits for Output Float Delay ...

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... LTC1854/LTC1855/LTC1856 DIAGRA S t (SDI Setup Time Before SCK ) SCK 2.4V SDI 0.4V t (SDO Valid Before BUSY , 2.4V BUSY 2.4V SDO 12 2.4V SCK SDI 18545 TD07 RD B15 SDO 18545 TD09 t (SDI Hold Time After SCK ) 2.4V 2.4V 0.4V 18545 TD08 t (BUS Relinquish Time) ...

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... ADC – and ADC DRIVING THE ANALOG INPUTS The input range for the LTC1854/LTC1855/LTC1856 is ±10V and the MUX inputs are overvoltage protected to ±30V. The input impedance is typically 31kW; therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a 3000pF capacitor at the input as shown in Figure 2 ...

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... The LTC1854/LTC1855/LTC1856 have an on-chip, tem- perature compensated, curvature corrected, bandgap ref- erence, which is factory trimmed to 2.50V. The full-scale range of the LTC1854/LTC1855/LTC1856 is equal to ±10V. The output of the reference is connected to the input of a gain of 1.6384x buffer through an 8k resistor (see Figure 3). The input to the buffer or the output of the reference is ...

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... LTC1856, between 01 1111 1111 1110 and 01 1111 1111 1111 for the LTC1855 and between 0111 1111 1110 and 0111 1111 1111 for the LTC1854. These adjustments as well as the factory trims affect all channels ...

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... Figures 6a and 6b show two different modes of operation for the LTC1856. For the 12-bit LTC1854 and 14-bit LTC1855, the last four and two bits of the SDO will output zeros, respectively. In mode 1 (Figure 6a tied low. The rising edge of CONVST starts the conversion. The data outputs are always enabled ...

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... U U APPLICATIO S I FOR ATIO LTC1854/LTC1855/LTC1856 W U 185456fa 17 ...

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... COM ( Figure 8. Examples of Multiplexer Options on the LTC1854/LTC1855/LTC1856 delayed by one conversion from the input word re- questing it. SDI SDI WORD 1 SDO SDO WORD 0 DATA TRANSFER INPUT DATA WORD The LTC1854/LTC1855/LTC1856 8-bit data word is clocked into the SDI input on the first eight rising SCK edges. ...

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... Don’t Care bits. POWER DOWN SELECTION (NAP, SLEEP) The last two bits of the input word (Nap and Sleep) deter- mine the power shutdown mode of the LTC1854/LTC1855/ LTC1856. See Table 2. Nap mode is selected when Nap = 1 and Sleep = 0. The previous conversion result will be clocked out and a conversion will occur before entering the Nap mode ...

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... LTC1854/LTC1855/LTC1856 U U APPLICATIO S I FOR ATIO 185456fa ...

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... AND DECOUPLING Wire wrap boards are not recommended for high resolu- tion or high speed A/D converters. To obtain the best performance from the LTC1854/LTC1855/LTC1856, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC ...

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... LTC1854/LTC1855/LTC1856 U U APPLICATIO S I FOR ATIO LTC1855/LTC1856 can be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply pins, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise op- eration of the ADC, and the foil width for these tracks should be as wide as possible ...

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... Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC1854/LTC1855/LTC1856 U G Package 28-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 1.25 ± ...

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... Configurable Unipolar/Bipolar Input 10V Single 5V Supply Programmable MUX and Sequencer, Parallel I/O Software-Selectable Spans, Pin Compatible with Single 5V Supply, 850mA with Autoshutdown Single 3V Supply, 450mA with Autoshutdown LTC1856/LTC1855/LTC1854 Software-Selectable Spans, ±1LSB INL/DNL DACs OUT ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade ...