ltc1867l Linear Technology Corporation, ltc1867l Datasheet - Page 13

• Manufacturer Part Number: ltc1867l
• Description: Ltc1863l - Micropower, 3v, 12-bit, 8-channel 175ksps Adcs
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
If the CS/CONV returns low during a bit decision, it can
create a small error. For best performance ensure that the
CS/CONV returns low either within 100ns after the conver-
sion starts (i.e. before the first bit decision) or after the
conversion ends. If CS/CONV is low when the conversion
ends, the MSB bit will appear on SDO at the end of the
conversion and the ADC will remain powered up.
Sleep Mode
If the SLP = 1 is selected in the input word, the ADC will
enter SLEEP mode and draw only leakage current (pro-
vided that all the digital inputs stay at GND or V
release from the SLEEP mode, the ADC needs 80ms to
wake up (charge the 2.2µF/10µF bypass capacitors on
V
Board Layout and Bypassing
To obtain the best performance, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside an
analog signal.
All analog inputs should be screened by GND. V
REFCOMP and V
plane as close to the pin as possible; the low impedance of
(LTC1867L)
(LTC1863L)
REF
CS/CONV
SDO
SDO
SCK
/REFCOMP pins).
SDI
Hi-Z
Hi-Z
Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV
Remaining HIGH after the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate
t
CONV
DD
U
should be bypassed to this ground
DON'T CARE
U
NAP MODE
W
MSB
MSB
D15 D14 D13
D11 D10
SD
U
1
DD
0S
). After
2
REF
S1
D9
3
,
D12
S0
D8
4
COM UNI SLP
D11 D10
D7
the common return for these bypass capacitors is essen-
tial to the low noise operation of the ADC. The width for
these tracks should be as wide as possible.
Timing and Control
Conversion start is controlled by the CS/CONV digital
input. The rising edge transition of the CS/CONV will start
a conversion. Once initiated, it cannot be restarted until the
conversion is complete. Figures 6 and 7 show the timing
diagrams for two types of CS/CONV pulses.
Example 1 (Figure 6) shows the LTC1863L/LTC1867L
operating in automatic nap mode with CS/CONV signal
staying HIGH after the conversion. Automatic nap mode
provides power reduction at reduced sample rate.
The ADCs can also operate with the CS/CONV signal
returning LOW before the conversion ends. In this mode
(Example 2, Figure 7), the ADCs remain powered up. The
digital output, SDO, will go HIGH immediately after the
conversion is complete if the analog inputs are above half
scale in unipolar mode or below half scale in bipolar mode.
This is a way to measure the conversion time of the A/D
converter.
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar mode.
5
D6
6
D9
D5
7
D8
D4
8
D7
D3
9
D6
LTC1863L/LTC1867L
D2
10
D5
D1
11
D4
D0
12
NOT NEEDED FOR LTC1863L
1/f
D3
13
DON'T CARE
SCK
D2
14
D1
15
D0
16
13
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