ltc1629-6 Linear Technology Corporation, ltc1629-6 Datasheet - Page 20

• Manufacturer Part Number: ltc1629-6
• Description: Polyphase, Synchronous Step-down Switching Regulator
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC1629-6
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1629-6 circuits: 1) LTC1629-6 V
(including loading on the differential amplifier output),
2) INTV
MOSFET transition losses.
1) The V
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the differential
amplifier output. V
(<0.1%) loss.
2) INTV
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV
ground. The resulting dQ/dt is a current out of INTV
is typically much larger than the control circuit current. In
continuous mode, I
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTV
from an output-derived source will scale the V
required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV
mately 3mA of V
loss from 10% or more (if the driver was powered directly
from V
20
%Efficiency = 100% – (L1 + L2 + L3 + ...)
IN
CC
CC
) to only a few percent.
IN
regulator current, 3) I
current is the sum of the MOSFET driver and
current has two components: the first is the
CC
IN
power through the EXTV
current. This reduces the mid-current
IN
U
GATECHG
current typically results in a small
U
CC
= (Q
current results in approxi-
2
T
R losses and 4) Topside
+ Q
W
B
), where Q
CC
switch input
U
IN
IN
T
current
current
and Q
CC
CC
that
to
B
3) I
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R
MOSFET can simply be summed with the resistances of L,
R
R
total resistance is 25m . This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as the
inverse square of V
and output power level. The combined effects of increas-
ingly lower output voltages and higher currents required
by high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4) Transition losses apply only to the topside MOSFET(s),
and only when operating at high input voltages (typically
20V or greater). Transition losses can be estimated from:
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and input fuse
resistance losses can be minimized by making sure that
C
switching frequency. A 50W supply will typically require a
minimum of 200 F to 300 F of capacitance having a
maximum of 10m
PolyPhase architecture typically halves to quarters this
input capacitance requirement over competing solutions.
Other losses including Schottky conduction losses during
dead-time and inductor core losses generally account for
less than 2% total additional loss.
IN
SENSE
DS(ON)
Transition Loss = (1.7) V
2
has adequate charge storage and a very low ESR at the
R losses are predicted from the DC resistances of the
and ESR to obtain I
=10m , R
L
OUT
=10m , and R
DS(ON)
to 20m
for the same external components
2
, then the resistance of one
IN
R losses. For example, if each
2
I
O(MAX)
of ESR. The LTC1629-6
SENSE
C
RSS
=5m , then the
f
SENSE
16296f
,