ltc1647-2 Linear Technology Corporation, ltc1647-2 Datasheet - Page 11

• Manufacturer Part Number: ltc1647-2
• Description: Dual Hot Swap Controllers
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
Power Supply Ramping
V
path (Figure 1). R1 provides load current fault detection
and R2 prevents MOSFET high frequency oscillation. By
ramping the gate of the pass transistor at a controlled rate
(dV/dt = 10 A/C1), the transient surge current
(I = C
backplane is limited to a safe value when the board is
inserted into the connector.
When power is first applied to V
A low-to-high transition at the ON pin initiates GATE ramp-
up. The rising dV/dt of GATE is set by 10 A/C1 (Figure 5),
where C1 is the total external capacitance between GATE
and GND. The ramp-up time for V
t = (V
V
CC
V
OUT
CC
+ V
+ V
LOAD
CC
is controlled by placing MOSFET Q1 in the power
GATE
V
V
GATE
0V
0V
CC
CC
V
V
•C1)/10 A.
0V
0V
CC
CC
•dV/dt = 10 A•C
Figure 5. Supply Turn-On/Off with ON
OUT OF UVLO
V
LKO
U
C
UNPLUGGED
LOAD
DISCHARGES
RAMP-UP
SLOPE = 10 A/C1
U
LOAD
V
V
CC
V
V
CC
GATE
RAMP-UP
SLOPE = 10 A/C1
ON
V
CC
/C1) drawn from the main
SLOPE = –50 A/C1
OUT
V
C
, the GATE pin pulls low.
OUT
LOAD
V
GATE
RAMP-DOWN
W
DISCHARGES
OUT
V
DUE TO V
GATE
INTO UVLO
V
LKO
FAST RAMP-DOWN
AT UNDERVOLTAGE
LOCKOUT
DROOP
is equal to
– V
CC
LKH
U
1647-1/2/3 F06
1647-1/2/3 F05
LTC1647-1/LTC1647-2/LTC1647-3
A high-to-low transition at the ON pin initiates a GATE
ramp-down at a slope of – 50 A/C1. This rate is usually
adequate as the supply bypass capacitors take time to
discharge through the load.
If the ON pin is connected to V
V
the undervoltage lockout threshold, V
the threshold is exceeded, GATE ramps at a controlled rate
of 10 A/C1. When the power supply is disconnected, the
body diode of Q1 holds V
GATE voltage droops at a rate determined by V
drops below V
GATE pulls down to GND.
Autoretry
The LTC1647-2 and LTC1647-3 are designed to allow an
automatic reset of the electronic circuit breaker after a
fault condition occurs. This is accomplished by pulling the
ON/FAULT (LTC1647-2) pin or the ON and FAULT pins tied
together (LTC1647-3) high through a resistor, R3, as
shown in Figure 7. An autoretry sequence begins if a fault
occurs. If the circuit breaker trips, FAULT pulls the ON pin
low. After a t
CC
(5V LOGIC)
is first applied, GATE is held low until V
FAULT
V
CC
V
0.1 F
ON
CC
– V
C3
V
V
SENSE
FAULT
RESET
GATE
LKO
Figure 7. Autoretry Sequence
R3
15k
– V
interval elapses, FAULT resets and R3
2
4
LKH
ON/FAULT
GND
V
CC
CC
, the LTC1647 enters UVLO and
1
0.01
about 700mV below V
R1
SENSE
CC
, or is pulled high before
8
LTC1647-2
IRF7413
LKO
t
GATE
RESET
Q1
6
t
t
RAMP
R2
10
DELAY
(Figure 6). Once
CC
1647-1/2/3 F07
+
rises above
CC
C1
10nF
C
OUT
LOAD
11
V
. If V
OUT
. The
CC