ad5160 Analog Devices, Inc., ad5160 Datasheet - Page 5

• Manufacturer Part Number: ad5160
• Description: 256-position Spi Compatible Digital Potentiometer
• Manufacturer: Analog Devices, Inc.

10
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(V
Table 3.
Parameter
SPI INTERFACE TIMING CHARACTERISTICS
NOTES
1
2
3
4
5
6
7
8
9
ABSOLUTE MAXIMUM RATINGS
(T
Table 4.
Parameter
V
V
I
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (T
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance
NOTES
1
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
MAX
Maximum terminal current is bounded by the maximum current handling of
Package power dissipation = (T
Typical specifications represent average readings at +25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
INL and DNL are measured at V
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
P
All dynamic characteristics use V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
DD
A
See timing diagram for location of measured values. All input control voltages are specified with t
level of 1.5 V.
AB
DISS
, V
A
DD
Clock Frequency
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
1
to GND
= V
= +25°C, unless otherwise noted.)
B
is calculated from (I
= +5V ± 10%, or +3V ± 10%; V
, V
DD
W
, Wiper (V
to GND
W
) = no connect.
2
θ
DD
JA
× V
: MSOP-10
DD
W
JMAX
). CMOS logic level inputs result in minimum power dissipation.
DD
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
= 5 V.
– T
A
)/θ
JMAX
JA
.
A
= V
)
Symbol
f
t
t
t
t
t
t
t
t
CLK
CH
DS
DH
CSS
CSW
CSH0
CSH1
CS1
6, 10
, t
DD
CL
; V
Value
–0.3 V to +7 V
V
±20 mA
0 V to +7 V
–40°C to +125°C
150°C
–65°C to +150°C
300°C
230°C/W
(Specifications Apply to All Parts)
DD
B
1
= 0 V; –40°C < T
Conditions
Clock level high or low
DD
= 5 V.
Rev. 0 | Page 5 of 16
A
< +125°C; unless otherwise noted.)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Min
5
5
15
40
0
0
10
20
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
Typ
1
Max
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
DD
and V
B
= 0 V.
AD5160