ad5501 Analog Devices, Inc., ad5501 Datasheet - Page 8

• Manufacturer Part Number: ad5501
• Description: High Voltage, 12-bit Voltage Output Dac
• Manufacturer: Analog Devices, Inc.

AD5501
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9, 10
11
12
13
14
15
16
Mnemonic
CLR
SYNC
SCLK
SDI
SDO
DGND
AGND
LDAC
NC
V
V
R_SEL
V
ALARM
V
FB
OUT
DD
LOGIC
Description
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the Input register and the DAC register are set to 0x000 and the outputs to zero-scale.
Falling edge Synchronization signal. This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following
clocks. The selected DAC register is updated following the 16th clock cycle unless SYNC is taken high before
this edge, in which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the
DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Serial Data Output. CMOS output. Serves as readback function for all DAC and Contol registers. Data is clocked
out on the rising edge of SCLK and is valid on the falling edge of SCLK.
Digital Ground Pin.
Analog Ground Pin.
Load DAC Input. Pulsing this pin low updates the DAC with the value in the Input register. If the LDAC pin is tied
low the DAC output is updated automatically when data is written to the Input register.
Not Connected. These pins should be left unconnected.
Voltage Feedback Pin. Feedback node for the output amplifier.
Buffered Analog Output Voltage from the DAC.
Range Select Pin. Tying this pin to DGND selects a DAC output range of 0V to 60 V, alternatively tying R_SEL to
VLOGIC select a DAC output range of 0V to 30 V.
Positive Analog Power Supply; 10V to 62V for the specified performance. This pin should be decoupled with
0.1μF ceramic capacitors and 10 μF capacitors.
An active low CMOS output pin. Flags an alarm if the temperature on the die exceeds 130ºC.
Logic Power Supply; 2.3V to 5.5V. This pin should be decoupled with 0.1μF ceramic capacitors and 10 μF
capacitors.
DGND
AGND
SYNC
LDAC
SCLK
SDO
CLR
SDI
1
2
3
4
5
6
7
8
Figure 5. TSSOP Configuration
(Not to Scale)
Rev. Pr B | Page 8 of 15
AD5501
TOP VIEW
15
14
13
12
11
10
16
9
ALARM
R_SEL
V
V
NC
NC
V
V
OUT
FB
LOGIC
DD
Preliminary Technical Data