cs1160 Shenzhen Chipsea Technologies CO., LTD, cs1160 Datasheet - Page 13

• Manufacturer Part Number: cs1160
• Description: Analog-to-digital A/d Converter
• Manufacturer: Shenzhen Chipsea Technologies CO., LTD

3 CS1160 FUNCTION MODULE DESCRIPTION
3.1
The input impedance of the CS1160 is about 5MΩ/PGA with the buffer off, but the input impedance
is up to about 5GΩ with the buffer on.
The buffer can be controlled by the BUF pin and the register ACR. When the BUF bit in ACR register
and BUF pin is high, the buffer is on.
The buffer will draw additional power dissipation when activated. The power depends on the PGA
setting. When PGA=1, the buffer produces approximately 50uA additional current; When the
PGA=128, the buffer produces approximately 150uA additional current.
The input range should be AGND+0.3V to AVDD-1.5V with the buffer on.
3.2
The Programmable Gain Amplifier (PGA) can be set to 1, 2, 4, 8, 16, 32, 64, or 128. Using PGA can
improve the ENOB of the A/D converter. For example, when PGA=1, the full scale input is 5V, the
converter can resolve down to 38.1uV; when PGA=128, the full scale input is 39mV, the converter
can resolve down to 300nV.
3.3
The Modulator of the CS1160 is a single loop, second order Sigma-Delta system. The sample
frequency of the modulator is controlled by the SPEED bit in ACR register (ACR bit 5). The sample
frequency is shown in Table8:
3.4
The CS1160 provides both self calibration and system calibration which include offset and gain
calibration of the A/D converter. During calibration, the DRDY signal will be held at high, which
indicates the result of the AD converter is invalid.
In order to ensure the accuracy of the data of the A/D converter, the calibration should be performed
after power-up, a change in temperature, or a change of the PGA.
At the completion of the calibration, the DRDY signal goes low, indicating the calibration is finished.
The first output data of the converter after calibration is invalid because of the delay of the inside
circuit, and the second output data is valid.
3.4.1
System calibration corrects the offset and gain errors of the chip and the system. When performing
system calibration, appropriate signal must be applied to the inputs. The commands of system
Copyright Reserved
Frequency
(MHz)
2.4576
4.9152
ANALOG INPUT BUFFER
PROGRAMMABLE GAIN AMPLIFIER (PGA)
MODULATOR
CALIBRATION
SYSTEM CALIBRATION
SPEED
0
1
0
1
Table 8
ADC Sample
Frequency
Shenzhen Chipsea Technologies CO., LTD.
19.200
38.400
19.200
(KHz)
9.600
The Sample Frequency of The Modulator
CS1160 Specification
www.chipsea.com
DR ＝ 00
7.5
15
30
15
Data Output Rate (Hz)
DR ＝ 01
3.75
7.5
7.5
15
DR ＝ 10
1.875
3.75
3.75
7.5
Frequency
Rejection
100/120
13 -24
50/60
25/30
50/60
(Hz)