cs87946aiyi Integrated Device Technology, cs87946aiyi Datasheet
cs87946aiyi
Manufacturer Part Number
cs87946aiyi
Description
Low Skew, ?1, ?2 Lvcmos Clock Generator
Manufacturer
Integrated Device Technology
Datasheet
1.CS87946AIYI.pdf
(9 pages)
B
87946AYI
G
clock inputs accept LVCMOS or LVTTL input levels. The low
impedance LVCMOS outputs are designed to drive 50 series
or parallel terminated transmission lines. The effective fanout
can be increased from 10 to 20 by utilizing the ability of the
outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87946I is characterized at 3.3V core/3.3V output. Guar-
anteed output and part-to-part skew characteristics make the
ICS87946I ideal for those clock distribution applications demand-
ing well defined performance and repeatability.
HiPerClockS™
DIV_SELC
DIV_SELA
DIV_SELB
,&6
CLK_SEL
LOCK
MR/nOE
ENERAL
CLK0
CLK1
D
The ICS87946I is a low skew, ÷1, ÷2 LVCMOS
Clock Generator and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS87946I has two select-
able single ended clock inputs. The single ended
IAGRAM
0
1
D
ESCRIPTION
1
2
0
1
0
1
0
1
www.icst.com/products/hiperclocks.html
QA0:QA2
QB0:QB2
QC0:QC3
1
P
F
• 10 single ended LVCMOS outputs, 7 typical output
• Selectable CLK0 and CLK1 LVCMOS clock inputs
• CLK0 and CLK1 can accept the following input levels:
• Maximum input/output frequency: 150MHz
• Output skew: 350ps (maximum)
• 3.3V input, 3.3V outputs
• -40°C to 85°C ambient operating temperature
• Pin compatible to the MPC946
impedance
LVCMOS and LVTTL
IN
EATURES
DIV_SELC
DIV_SELA
DIV_SELB
CLK_SEL
A
CLK0
CLK1
SSIGNMENT
GND
V
DD
1
2
3
4
5
6
7
8
LVCMOS C
32 31 30 29 28 27 26 25
7mm x 7mm x 1.4mm
9 10 11 12 13 14 15 16
32-Lead LQFP
Y Package
Top View
L
OW
LOCK
ICS87946I
S
REV. B OCTOBER 27, 2008
KEW
24
23
22
21
20
19
18
17
G
ENERATOR
, 1, 2
GND
QB0
V
QB1
GND
QB2
V
V
DDB
DDB
DDC
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cs87946aiyi Summary of contents
Page 1
G D ENERAL ESCRIPTION The ICS87946I is a low skew, ÷1, ÷2 LVCMOS ,&6 Clock Generator and a member of the HiPerClockS™ family of High Performance Clock HiPerClockS™ Solutions from ICS. The ICS87946I has two select- able single ended clock ...
Page 2
ABLE IN ESCRIPTIONS ...
Page 3
BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs, V DDx Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS ...
Page 4
ABLE HARACTERISTICS ...
Page 5
P ARAMETER 1.65V±0.15V DD DDx LVCMOS GND = -1.65V±0.15V 3. UTPUT OAD EST IRCUIT V PART PART tsk(pp ...
Page 6
ABLE VS IR LOW ABLE q Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to ...
Page 7
ACKAGE UTLINE UFFIX ABLE Reference Document: ...
Page 8
ABLE RDERING NFORMATION ...
Page 9
...