cs8413-cs Cirrus Logic, Inc., cs8413-cs Datasheet - Page 13

• Manufacturer Part Number: cs8413-cs
• Description: 96 Khz Digital Audio Receivers
• Manufacturer: Cirrus Logic, Inc.

and output random data if ROER is not set. The
conditions that activate ERF are those reported in
SR2 and enabled in IER2. Figure 10 illustrates the
modes selectable by SDF2-SDF0 and FSF1-FSF0.
MSTR, which in most applications will be set to
one, determines whether FSYNC and SCK are out-
puts (MSTR = 1) or inputs (MSTR = 0). When
FSYNC and SCK are inputs (slave mode) the audio
DS240F1
FSF
SPECIAL MODES:
SDF
210 MSTR
10 (bit)
00
01
10
11
00
01
10
11
SDF
210 (bit)
000
001
011
101
111
010*† 1
100*
100
110
010
* Error flags are not accurate in these modes
† FSYNC is inverted FSF = 11
MSTR
1
1
1
1
0
0
0
0
1
0
0
0
FSYNC Output
FSYNC Output
FSYNC Output
FSYNC Output
MSB First - 32
MSB Last
LSB Last - 16
LSB Last - 18
LSB Last - 20
NRZ Data
Bi-Phase Data
FSYNC Input
FSYNC Input
FSYNC Input
FSYNC Input
Async SCK
MSB First - 24
MSB First - 16
Name
Name
MSB
LSB
LSB
LSB
Figure 10. CS8413 Serial Port SDATA and FSYNC Timing
MSB
MSB
MSB
MSB
16 Clocks
16 Clocks
AUX
24 Bits, Incl. Aux
24 Bits, Incl. Aux
Left Sample
MSB
LSB
32 Clocks
24 Bits, Incl. Aux
32 Clocks
Bi-Phase Mark Data
LSB
MSB
32 Bits
32 Bits
16 Bits
24 Bits, Incl. Aux
MSB
20 Bits
18 Bits
16 Clocks
16 Clocks
LSB
LSB
16 Bits
MSB
data can be read twice or missed if the device con-
trolling FSYNC and SCK is on a different time-
base than the CS8413. If the audio data is read
twice or missed, the SLIP bit in SR1 is set. SCED
selects the SCK edge to output data on. SCED high
causes data to be output on the falling edge, and
SCED low causes data to be output on the rising
edge.
VUCP
MSB
LSB
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB
AUX
24 Bits, Incl. Aux
24 Bits, Incl. Aux
Right Sample
MSB
LSB
24 Bits, Incl. Aux
Bi-Phase Mark Data
LSB
32 Clocks
16 Bits
MSB
32 Bits
32 Bits
24 Bits, Incl. Aux
32 Clocks
MSB
CS8413 CS8414
20 Bits
18 Bits
16 Bits
LSB
LSB
MSB
VUCP
MSB
LSB
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB
AUX
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