cs4412a Cirrus Logic, Inc., cs4412a Datasheet - Page 13

• Manufacturer Part Number: cs4412a
• Description: 30w Quad Half-bridge Digital Amplifier Power Stage
• Manufacturer: Cirrus Logic, Inc.

DS786A2
4. APPLICATIONS
4.1
4.2
4.2.1
WARNING: The Popguard feature can not be used for the CS4412A in applications where VP exceeds 12 V. Doing
Overview
The CS4412A is a high-efficiency power stage for digital Class-D amplifiers designed to be configured as
four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or
one parallel full-bridge channel.
The CS4412A integrates on-chip over-current, under-voltage, over-temperature protection and error report-
ing as well as a thermal warning indicator. The low R
delivering
and no external heat sink.
Reset and Power-Up
Reliable power-up can be accomplished by keeping the device in reset until the power supplies and config-
uration pins are stable. It is also recommended that the RST12 and RST34 pins be activated if the voltage
supplies drop below the recommended operating condition to prevent power-glitch related issues.
When the RST12 or RST34 are low, the corresponding channels of the CS4412A enter a low-power mode.
All of the channels’ internal states are reset, and the corresponding power output pins are held in a high-
impedance state. When RST12 or RST34 are high, the corresponding outputs begin normal operation ac-
cording to the RAMP, CNFG[2:0], and IN1 - IN4 pins.
PWM Popguard Transient Control
The CS4412A uses PWM Popguard technology to minimize the effects of output transients during power-
up and power-down for half-bridge configurations. This technique reduces the audio transients commonly
produced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors
connected in series with the audio outputs.
When the device is configured for ramping (RAMP set high) and RST12 or RST34 is set high, the corre-
sponding power outputs will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time
for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up tran-
sient. The corresponding outputs will not begin normal operation until the ramp has reached the bias point.
The time it takes to complete a ramp-up sequence will vary slightly from the applied VP voltage; typical
ramp-up speeds achieved with a 1000 µF DC blocking capacitor are listed in
with the value of the capacitor.
so could result in permanent damage to the CS4412A. The RAMP pin must always be tied low in ap-
plications where VP exceeds 12 V.
85%
efficiency. This efficiency provides for a smaller device package, smaller power supplies,
* With 1000 µF DC Blocking Capacitor.
Table 2. Typical Ramp Times for Typical VP Voltages
VP Voltage
12 V
8 V
DS(ON)
Typical Ramp Time*
outputs can source up to
2.20 seconds
1.25 seconds
Table
2. These times scale
2.5 A
CS4412A
peak current,
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