cs4227 Cirrus Logic, Inc., cs4227 Datasheet - Page 12

• Manufacturer Part Number: cs4227
• Description: Six Channel, 20-bit Codec
• Manufacturer: Cirrus Logic, Inc.

2. FUNCTIONAL DESCRIPTION
2.1
The CS4227 has 2 channels of 20-bit analog-to-
digital conversion and 6 channels of 20-bit digital-
to-analog conversion. A mono 20-bit ADC is also
provided. All ADCs and DACs are delta-sigma
converters. The stereo ADC inputs have adjustable
input gain, while the DAC outputs have adjustable
output attenuation.
Digital audio data received by the DACs and trans-
mitted from the ADCs is communicated over sepa-
rate serial ports, allowing concurrent writing to and
reading from the device. The CS4227 functions are
controlled via a serial microcontroller interface.
Figure 1 shows the recommended connection dia-
gram for the CS4227.
2.2
2.2.1
AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L
and AINAUX are the line level input pins (See Fig-
ure 5). These pins are internally biased to the
CMOUT voltage (nominally 2.3 V). A 10 µF DC
blocking capacitor allows signals centered around
0 V to be input. Figure 6 shows an optional dual op
amp buffer which combines level shifting with a
gain of 0.5 to attenuate the standard line level of
2 V
used to bias the op-amps to approximately one half
the supply voltage. With this input circuit, the
10 µF DC blocking caps in Figure 5 may be omit-
ted. Any remaining DC offset will be removed by
the internal high-pass filters.
Selection of the stereo input pair for the 20-bit
ADC's is accomplished by setting the AIS1/0 bits,
which are accessible in the ADC Control Byte. On-
chip anti-aliasing filters follow the input mux, pro-
viding anti-aliasing for all input channels.
12
rms
Overview
Analog Inputs
to 1 V
Line Level Inputs
rms
. The CMOUT reference level is
The analog inputs may also be configured as differ-
ential inputs. This is enabled by setting bits
AIS1/0 = 3. In the differential configuration, the
left channel inputs reside on pins 10 and 11, and the
right channel inputs reside on pins 12 and 13 as de-
scribed in the table below. In differential mode, the
full scale input level is 2 V
The analog signal is input to the mono ADC via the
AINAUX pin.
Independent Muting of both the stereo ADC's and
the mono ADC is possible through the ADC Con-
trol Byte (#11) with the MUTR, MUTL and
MUTM bits.
AIN3L
AIN3R
AIN2L
AIN2R
AIN1L
AIN1R
Op-Amps are
MC34074 or
Single-ended
MC33078
Example
Table 1. Single-ended vs Differential Input Pin
Line In
Right
Line In
Left
Figure 6. Optional Line Intput Buffer
3.3 F
3.3 F
0.47 F
20 k
20 k
Pin 10
Pin 9
Pin 11
Pin 12
Pin 14
Pin 13
Assignments
Pin #
-
+
+
-
10 k
10 k
100 pF
100 pF
5 k
rms
AINL+
unused
AINL-
AINR-
unused
AINR+
.
Differential Inputs
CS4227
DS281PP2
CMOUT
AINxL
AINxR