hrf-at4521 Honeywell International's Solid State Electronics Center (SSEC), hrf-at4521 Datasheet - Page 3

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hrf-at4521

Manufacturer Part Number
hrf-at4521
Description
31.0 Db, Dc - 2.5ghz, 5 Bit Serial Digital Attenuator
Manufacturer
Honeywell International's Solid State Electronics Center (SSEC)
Datasheet

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HRF- AT4521
PIN CONFIGURATIONS
Note: Bottom ground plate must be grounded for proper RF performance.
SERIAL DATA LOAD
Serial data is shifted into the register on the rising edge of clock, MSB first. The state of “OE” will not affect the shifting of
data. The rising edge of the “OE” signal will be the clock for the transfer of shifted data. Latched new data occurs one
prop delay after the rising edge of “OE”. See the Electrical Spec Table for AC parameters.
TRUTH TABLE
Operation: Data on serial input D is clocked into internal registers on the low to high transition of the Clock signal (CK).
The register output is enabled when Output Enable (OE) is in the low state.
www.honeywell.com/microwave
Pin
1
2
3
4
5
6
7
8
S4
0
0
0
0
0
1
1
Function
RF INPUT
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
VDD
S3
0
0
0
0
1
0
1
Pin
11
12
13
14
15
16
10
9
S2
0
0
0
1
0
0
1
RF OUTPUT
Function
GROUND
GROUND
GROUND
DATA
VSS
CLK
OE
S1
0
0
1
0
0
0
1
S0
0
1
0
0
0
0
1
Reference Input
Output
16 dB
31 dB
"0" = CMOS Low, "1" = CMOS High.
1 dB
2 dB
4 dB
8 dB
3

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