MC74VHCT74ADTR2 ON Semiconductor, MC74VHCT74ADTR2 Datasheet

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MC74VHCT74ADTR2

Manufacturer Part Number
MC74VHCT74ADTR2
Description
IC FLIP FLOP DUAL D S/R 14-TSSOP
Manufacturer
ON Semiconductor
Series
74VHCTr
Type
D-Typer
Datasheet

Specifications of MC74VHCT74ADTR2

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
160MHz
Delay Time - Propagation
6.3ns
Trigger Type
Positive Edge
Current - Output High, Low
8mA, 8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
MC74VHCT74A
Dual D-Type Flip-Flop
with Set and Reset
flip−flop fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
during the positive going transition of the Clock pulse.
accomplished by setting the appropriate input Low.
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 6
RD1
CP1
SD1
D1
The MC74VHCT74A is an advanced high speed CMOS D−type
The signal level applied to the D input is transferred to Q output
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
The internal circuit is composed of three stages, including a buffer
The VHCT inputs are compatible with TTL levels. This device can
The VHCT74A input structures provide protection when voltages
High Speed: f
Low Power Dissipation: I
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Low Noise: V
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 128 FETs or 32 Equivalent Gates
Pb−Free Packages are Available
1
2
3
4
max
Figure 2. Logic Diagram
OLP
= 60 MHz (Typ) at V
= 0.8 V (Max)
5
6
Q1
Q1
CC
= 2 mA (Max) at T
RD2
CP2
SD2
D2
CC
13
12
11
10
= 5.0 V
A
= 25°C
CC
= 0 V. These
9
8
1
Q2
Q2
*Both outputs will remain high as long as Set and Reset
See detailed ordering and shipping information on page 3 of
this data sheet.
A
WL, L
Y
WW, W = Work Week
G or G
(Note: Microdot may be in either location)
are low, but the output states are unpredictable if Set
and Reset go high simultaneously.
1
1
SD
H
H
H
H
H
H
L
L
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
ORDERING INFORMATION
Figure 1. Pin Assignment
GND
CASE 751A
CASE 948G
RD1
CP1
SD1
DT SUFFIX
TSSOP−14
D SUFFIX
RD
Q1
Q1
SOIC−14
D1
http://onsemi.com
H
H
H
H
H
H
L
L
FUNCTION TABLE
Inputs
1
2
3
4
5
6
7
CP
X
X
X
H
L
Publication Order Number:
MARKING DIAGRAMS
14
1
D
X
X
H
X
X
X
X
L
14
13
12
10
11
14
9
8
1
MC74VHCT74A/D
VHCT74AG
AWLYWW
V
RD2
D2
CP2
SD2
Q2
Q2
No Change
No Change
No Change
ALYWG
VHCT
CC
H*
Outputs
Q
H
H
L
L
74A
G
H*
Q
H
H
L
L

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MC74VHCT74ADTR2 Summary of contents

Page 1

MC74VHCT74A Dual D-Type Flip-Flop with Set and Reset The MC74VHCT74A is an advanced high speed CMOS D−type flip−flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power ...

Page 2

MAXIMUM RATINGS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

... ORDERING INFORMATION Device MC74VHCT74AD MC74VHCT74ADR2 MC74VHCT74ADR2G MC74VHCT74ADT MC74VHCT74ADTR2 MC74VHCT74ADTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. (Input 3.0ns Î ...

Page 4

CP 1 1/f max t t PLH PHL 1 Figure 3. Switching Waveform VALID 1 1 Figure 5. Switching Waveform INPUT Figure 7. Input Equivalent ...

Page 5

G −T− SEATING 14 PL PLANE 0.25 (0.010 PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE 0.25 (0.010 ...

Page 6

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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