MD3331-D64 ETC-unknow, MD3331-D64 Datasheet - Page 65

• Manufacturer Part Number: MD3331-D64
• Description: Diskonchip Millennium Plus
• Manufacturer: ETC-unknow

10.4.4 Write Cycle Timing Multiplexed Interface
65
1. CE# may be asserted any time before or after WE# is asserted. If CE# is asserted after WE#, all timing relative to WE# asserted will be
referenced instead to the time of CE# asserted.
2. CE# may be negated any time before or after WE# is negated. If CE# is negated before WE#, all timing relative to WE# negated will be
referenced instead to the time of CE# negated.
3. WE# may be asserted before or after the rising edge of AVD#. The beginning of the WE# asserted pulse width spec is measured from the
later of the falling edge of WE# or the rising edge of AVD#.
tsu(AVD-WE)
Trec(WE-AVD)
tsu(CE0)
tho(CE0)
tho(AVD)
tsu(AVD)
Tw(AVD)
tho(CE1)
tsu(CE1)
trec(WE)
Symbol
tw(WE)
Tsu(D)
Tho(D)
Twcyc
1
2
1
AD[15:0]
Address to AVD#
Address to AVD#
AVD# low pulse width
AVD#
WE#
WE# asserted width (RAM)
WE# asserted width (all other addresses)
Write Cycle Time
CE#
WE#
OE# or WE#
CE#
WE#
D to WE#
WE#
AVD#
WE#
OE#
CE#
to WE#
to WE#
to AVD#
to CE#
to start of next cycle
to D hold time
Table 22: Multiplexed Interface Write Cycle Parameters
to WE#
T
Figure 27: Multiplexed Interface Write Cycle Timing
HO
T
SU
(CE1)
setup time (RAM)
(AVD)
Description
to CE#
setup time
hold time
or OE#
ADDR
Tw(AVD)
setup time
in next cycle
setup time
hold time
T
T
T
SU
SU
Data Sheet, Rev. 1.7
HO
hold time
3
(AVD-WE)
(CE0)
(AVD)
setup time
T
WCYC
Tw(WE)
DATA
T
VCC=2.7-3.6V
SU
VCCQ=VCC
Min
12
28
48
49
79
20
27
(D)
—
—
T
5
7
4
6
6
0
HO
(CE0)
Max
16MB (128Mb)
DiskOnChip Millennium Plus 16/32/64MByte
T
T
HO
T
REC
REC
(D)
T
(WE)
SU
(WE-AVD)
(CE1)
VCCQ=1.65-1.9V
Min
VCC=2.7-3.6V
12
30
47
48
79
20
28
—
—
NEXT ADDR
5
7
4
6
6
0
Max
93-SR-002-03-8L
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns