NJU26126 New Japan Radio Co.,Ltd, NJU26126 Datasheet - Page 7

• Manufacturer Part Number: NJU26126
• Description: Digital Signal Processor For Tv
• Manufacturer: New Japan Radio Co.,Ltd

Note :
Ver.2010-08-19
1.4 Reset
To initialize the NJU26126, RESETb pin should be set Low level during some period. After some period of
Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26126. After
the power supply and the oscillation of the NJU26126 becomes stable, RESETb pin must be kept
Low-level more than t
After RESETb pin level goes to "High" (after reset release), a setup of the internal hardware of a Serial
Host Interface completes NJU26126 within 10msec. Then, it will be in the state which can communicate.
All the I/O terminals and the Open-Drain I/O terminals compulsorily enter the state of the high-impedance
when it is made RESETb=Low. However, the pull-up/pull-down of the terminal that has adhered the
pull-up/pull-down is effective.
Don’t stop the supply of a clock while operating. NJU26126 installs PLL circuit internally. If the supply of a
clock is stopped, PLL circuit cannot be sent a clock to the inside and NJU26126 does not operate normally.
If supply of a clock is stopped or the NJU26126 is reset again, putting a normal clock into CLK terminal, the
period RESETb terminal of t
from initial setting.
RESETb
V
CLK
V
REGO
DD
RESETb
period. (Fig.5)
RESETb
t
VREGO
Table 4 Reset Time
Fig.5 Reset Timing
is kept “Low” level.(Table 4) Next, the NJU26126 is reset. Then redo
Symbol
t
t
RESETb
VREGO
OSC unstable
Time
1.0msec
10msec
t
RESETb
OSC stable
NJU26126
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