MD51V65165E Oki Semiconductor, MD51V65165E Datasheet - Page 8

• Manufacturer Part Number: MD51V65165E
• Description: 4,194,304-word 16-bit Dynamic Ram Fast Page Mode Type With Edo
• Manufacturer: Oki Semiconductor

Notes: 1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization
1
Semiconductor
2. The AC characteristics assume t
3. V
4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100pF.
5. Operation within the t
6. Operation within the t
7. t
8. t
9. t
10. t
11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to
12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier.
13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.
14. t
15. t
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
are measured between V
The output timing reference levels are V
t
then the access time is controlled by t
t
then the access time is controlled by t
open circuit condition and are not referenced to output voltage levels.
sheet as electrical characteristics only. If t
the data out will remain open circuit (high impedance) throughout the entire cycle. If t
(Min.), t
write cycle and data out will contain data read from the selected cell; if neither of the above sets of
conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
the WE leading edge in an OE control write cycle, or a read modify write cycle.
RCD
RAD
CEZ
CEZ
RCH
WCS
CWL
CP
IH
is determined by the time both UCAS and LCAS are high.
, and t
(Min.) and V
(Max.), t
, t
(Max.) is specified as a reference point only. If t
(Max.) is specified as a reference point only. If t
or t
should be satisfied by both UCAS and LCAS.
CWD
RRH
RWD
REZ
, t
RWD
must be satisfied for a read cycle.
REZ
must be satisfied for open circuit condition.
t
RWD
, t
(Max.), t
IL
AWD
(Max.) are reference levels for measuring input timing signals. Transition times (t
(Min.), t
RCD
RAD
and t
IH
WEZ
(Max.) limit ensures that t
(Max.) limit ensures that t
CPWD
and V
AWD
(Max.), and t
T
are not restrictive operating parameters. They are included in the data
IL
t
= 2ns.
AWD
.
CAC
AA
(Min.) and t
.
OH
.
WCS
OEZ
=2.0 and V
(Max.) define the time at which the output achieved the
t
WCS
CPWD
RAC
RCD
RAC
RAD
(Min.), then the cycle is an early write cycle and
OL
(Max.) can be met.
is greater than the specified t
(Max.) can be met.
is greater than the specified t
=0.8V.
t
CPWD
(Min.), then the cycle is a read modify
FEDD51V65165E-02
MD51V65165E
RAD
RCD
(Max.) limit,
(Max.) limit,
CWD
t
8/16
CWD
T
)