S25FL008K Meet Spansion Inc., S25FL008K Datasheet - Page 33

• Manufacturer Part Number: S25FL008K
• Description: 8-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

July 30, 2010 S25FL008K_00_01
6.2.15
6.2.16
Continuous Read Mode Bits (M7-0)
Continuous Read Mode Reset (FFh or FFFFh)
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad I/O”,
“Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random Flash
memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place) to be
performed on serial flash devices.
M7-0 need to be set by the Dual/Quad I/O Read instructions. M5-4 are used to control whether the 8-bit SPI
instruction code (BBh, EBh, E7h or E3h) is needed or not for the next command. When M5-4 = (1,0), the next
command will be treated same as the current Dual/Quad I/O Read command without needing the 8-bit
instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all commands can
be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used.
Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the
Continuous Read Mode and return to normal SPI operation, as shown in
Since S25FL008K does not have a hardware Reset pin, so if the controller resets while S25FL008K is set to
Continuous Mode Read, the S25FL008K will not recognize any initial standard SPI instructions from the
controller. To address this possibility, it is recommended to issue a Continuous Read Mode Reset instruction
as the first instruction after a system Reset. Doing so will release the device from the Continuous Read Mode
and allow Standard SPI instructions to be recognized.
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The instruction is
“FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in
instruction “FFFFh”.
CS#
CLK
IO1
IO3
IO0
IO2
D a t a
Mode 3
Mode 0
S h e e t
Figure 6.21 Continuous Read Mode Reset for Fast Read Dual/Quad I/O
0
( A d v a n c e
1
Mode Bit Reset
for Quad I/O
2
FFh
3
S25FL008K
4
I n f o r m a t i o n )
5
6
Don’t Care
Don’t Care
Don’t Care
7
8
9
10
11
Mode Bit Reset
for Quad I/O
FFh
Figure
12
13
6.21.
14
15
Mode 3
Mode 0
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