SST39VF6401 Silicon Storage Technology, Inc., SST39VF6401 Datasheet - Page 4

• Manufacturer Part Number: SST39VF6401
• Description: 64 Mbit X16 Multi-purpose Flash Plus
• Manufacturer: Silicon Storage Technology, Inc.

EOL Data Sheet
Data Protection
The SST39VF640x provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST39VF6402 support top hardware block protection,
which protects the top 32 KWord block of the device. The
SST39VF6401 support bottom hardware block protection,
which protects the bottom 32 KWord block of the device.
The Boot Block address ranges are described in Table 2.
Program and Erase operations are prevented on the 32
KWord when WP# is low. If WP# is left floating, it is inter-
nally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations on
that block.
TABLE 2: Boot Block Address Ranges
©2008 Silicon Storage Technology, Inc.
Product
Bottom Boot Block
Top Boot Block
DD
SST39VF6401
SST39VF6402
Power Up/Down Detection: The Write operation is
DD
is less than 1.5V.
3F8000H-3FFFFFH
000000H-007FFFH
Address Range
T2.0 1223(03)
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
4
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T
required after RST# is driven high before a valid Read can
take place (see Figure 16).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF640x provide the JEDEC approved Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of the three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte
sequence. These devices are shipped with the Software
Data Protection permanently enabled. See Table 6 for the
specific software command codes. During SDP command
sequence, invalid commands will abort the device to read
mode within T
V
sequence.
Common Flash Memory Interface (CFI)
The SST39VF640x also contain the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as product ID entry command with 98H
(CFI Query command) to address 5555H in the last byte
sequence. Once the device enters the CFI Query mode,
the system can read CFI data at the addresses given in
Tables 7 through 9. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.
IH
, but no other value, during any SDP command
RP ,
RC.
SST39VF6401 / SST39VF6402
any in-progress operation will terminate and
The contents of DQ
15
-DQ
S71223(03)-00-EOL
8
can be V
RHR
IL
6/08
or
is